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[Submitted] alpha: Check interrupts before quiesce
|
ahansson
|
August 5th, 2013, 8:35 a.m.
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[Submitted] mem: Perform write merging in the DRAM write queue
|
ahansson
|
August 5th, 2013, 4:55 p.m.
|
|
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[Submitted] cpu: Fix a bug in the O3 CPU introduced by the cache line patch
|
ahansson
|
August 7th, 2013, 3:12 p.m.
|
|
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[Submitted] mem: Change AbstractMemory defaults to match the common case
|
ahansson
|
July 19th, 2013, 8:33 a.m.
|
|
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[Submitted] cpu: Fix TrafficGen trace playback
|
ahansson
|
July 18th, 2013, 1:17 p.m.
|
|
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[Submitted] mem: Use STL deque in favour of list for DRAM queues
|
ahansson
|
July 18th, 2013, 12:59 p.m.
|
|
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[Submitted] power: Add voltage domains to the clock domains
|
ahansson
|
June 27th, 2013, 4:40 p.m.
|
|
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[Submitted] stats: Fix issue when printing 2D vectors
|
ahansson
|
July 16th, 2013, 7:44 a.m.
|
|
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|
[Submitted] config: Move the memory instantiation outside FSConfig
|
ahansson
|
July 15th, 2013, 8:42 a.m.
|
|
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[Submitted] mem: Add an internal packet queue in SimpleMemory
|
ahansson
|
July 12th, 2013, 2:04 p.m.
|
|
|
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[Submitted] mem: Allow disabling of tXAW through a 0 activation limit
|
ahansson
|
July 12th, 2013, 9:46 a.m.
|
|
|
|
[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (2/2)
|
ahansson
|
August 19th, 2013, 9:41 a.m.
|
|
|
|
[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (1/2)
|
ahansson
|
August 19th, 2013, 9:39 a.m.
|
|
|
|
[Discarded] config: Change default memory size to 256 MB
|
ahansson
|
July 5th, 2013, 1:18 p.m.
|
|
|
|
[Submitted] cpu: Move the branch predictor out of the BaseCPU
|
ahansson
|
August 19th, 2013, 9:38 a.m.
|
|
|
|
[Submitted] arch: Resurrect the NOISA build target and rename it NULL
|
ahansson
|
August 19th, 2013, 9:42 a.m.
|
|
|
|
[Submitted] util: Add colours to the dot output
|
ahansson
|
August 19th, 2013, 9:33 a.m.
|
|
|
|
[Submitted] tests: Move ISA-independent tests to the NULL ISA
|
ahansson
|
August 19th, 2013, 9:43 a.m.
|
|
|
|
[Submitted] scons: Enable build on OSX
|
ahansson
|
August 19th, 2013, 9:30 a.m.
|
|
|
|
[Submitted] arch: Header clean up for NOISA resurrection
|
ahansson
|
August 19th, 2013, 9:38 a.m.
|
|
|
|
[Submitted] alpha: Move system virtProxy to Alpha only
|
ahansson
|
August 19th, 2013, 9:34 a.m.
|
|
|
|
[Submitted] util: Add ini string as tooltip info in dot output
|
ahansson
|
August 19th, 2013, 9:33 a.m.
|
|
|
|
[Submitted] util: Add class name to dot graph and output to svg
|
ahansson
|
August 19th, 2013, 9:32 a.m.
|
|
|
|
[Submitted] swig: Fix issue with circular import in 2.0.9/2.0.10
|
ahansson
|
September 6th, 2013, 7:22 a.m.
|
|
|
|
[Submitted] swig: Warn on use of incompatible swig/gcc combinations
|
ahansson
|
September 6th, 2013, 9:59 a.m.
|
|
|
|
[Submitted] ext: Fix fputils compiler flags to ensure ISO C99
|
ahansson
|
October 1st, 2013, 8:58 a.m.
|
|
|
|
[Submitted] kvm: Only include KVM support for supported kernels
|
ahansson
|
September 30th, 2013, 5:34 p.m.
|
|
|
|
[Submitted] mem: Fixes for DRAM stats accounting
|
ahansson
|
October 31st, 2013, 9:46 a.m.
|
|
|
|
[Submitted] mem: Fix DRAM bank occupancy for streaming access
|
ahansson
|
October 16th, 2013, 7:39 a.m.
|
|
|
|
[Submitted] test: Use SimpleMemory for atomic full-system tests
|
ahansson
|
October 17th, 2013, 5:31 p.m.
|
|
|
|
[Submitted] sim: Clarify the difference between tracing and debugging
|
ahansson
|
October 17th, 2013, 5:37 p.m.
|
|
|
|
[Submitted] mem: Fix the LPDDR3 page size
|
ahansson
|
October 16th, 2013, 7:50 a.m.
|
|
|
|
[Submitted] mem: Adding stats for DRAM power calculation
|
ahansson
|
October 16th, 2013, 7:49 a.m.
|
|
|
|
[Submitted] mem: Unify request selection for read and write queues
|
ahansson
|
October 16th, 2013, 7:48 a.m.
|
|
|
|
[Submitted] mem: Add a simple adaptive version of the open-page policy
|
ahansson
|
October 16th, 2013, 7:47 a.m.
|
|
|
|
[Submitted] mem: Just-in-time write scheduling in DRAM controller
|
ahansson
|
October 16th, 2013, 7:45 a.m.
|
|
|
|
[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
|
|
[Submitted] mem: Less conservative tRAS in DRAM configurations
|
ahansson
|
October 16th, 2013, 7:43 a.m.
|
|
|
|
[Submitted] mem: Make tXAW enforcement less conservative and per rank
|
ahansson
|
October 16th, 2013, 7:42 a.m.
|
|
|
|
[Submitted] mem: Pick the next DRAM request based on bank availability
|
ahansson
|
October 16th, 2013, 7:41 a.m.
|
|
|
|
[Submitted] mem: Use the same timing calculation for DRAM read and write
|
ahansson
|
October 16th, 2013, 7:40 a.m.
|
|
|
|
[Submitted] mem: Schedule time for DRAM event taking tRAS into account
|
ahansson
|
October 16th, 2013, 7:38 a.m.
|
|
|
|
[Submitted] mem: Add tRAS parameter to the DRAM controller model
|
ahansson
|
October 16th, 2013, 7:36 a.m.
|
|
|
|
[Submitted] cpu: Fix Checker register index use
|
ahansson
|
November 5th, 2013, 4:34 p.m.
|
|
|
|
[Submitted] mem: Fix bug in PhysicalMemory use of mmap and munmap
|
ahansson
|
February 13th, 2014, 2:41 p.m.
|
|
|
|
[Submitted] mem: Filter cache snoops based on address ranges
|
ahansson
|
January 23rd, 2014, 8:23 a.m.
|
|
|
|
[Submitted] dev: Include basic devices in NULL ISA build
|
ahansson
|
February 13th, 2014, 2:39 p.m.
|
|
|
|
[Submitted] ruby: Simplify RubyPort flow control and routing
|
ahansson
|
October 10th, 2013, 7:49 a.m.
|
|
|
|
[Discarded] ruby: Add bridges between RubyPort and NoncoherentBus
|
ahansson
|
January 23rd, 2014, 5:33 p.m.
|
|
|
|
[Submitted] mem: Edit proto Packet and enhance the python script
|
ahansson
|
February 21st, 2014, 1:30 p.m.
|
|
