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[Submitted] mem: Fix a bug in the cache port flow control
|
ahansson
|
August 27th, 2014, 4:15 p.m.
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[Submitted] mem: Fix address interleaving bug in DRAM controller
|
ahansson
|
August 13th, 2014, 12:49 p.m.
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[Submitted] mem: Fix bug in DRAM bytes per activate
|
ahansson
|
March 7th, 2014, 11:42 p.m.
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[Submitted] mem: Fix bug in PhysicalMemory use of mmap and munmap
|
ahansson
|
February 13th, 2014, 2:41 p.m.
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[Submitted] mem: Fix bug relating to writebacks and prefetches
|
ahansson
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December 12th, 2014, 5:49 p.m.
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[Submitted] mem: Fix cache MSHR conflict determination
|
ahansson
|
February 23rd, 2015, 1:05 p.m.
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[Submitted] mem: Fix cache sender state handling and add clarification
|
ahansson
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December 9th, 2015, 11:51 p.m.
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[Submitted] mem: Fix CommMonitor style and response check
|
ahansson
|
June 4th, 2013, 10:47 a.m.
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[Submitted] mem: Fix DRAM bank occupancy for streaming access
|
ahansson
|
October 16th, 2013, 7:39 a.m.
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[Submitted] mem: Fix DRAM draining to ensure write queue is empty
|
ahansson
|
November 7th, 2012, 12:25 a.m.
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[Submitted] mem: Fix event scheduling issue for prefetches
|
ahansson
|
December 12th, 2014, 5:49 p.m.
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[Submitted] MEM: Fix fs.py by specifying the range size rather than end
|
ahansson
|
January 24th, 2012, 5:08 a.m.
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[Submitted] mem: Fix incorrect assert failure in the Cache
|
ahansson
|
February 26th, 2014, 10:52 a.m.
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[Submitted] mem: Fix initial value problem with MemChecker
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] MEM: Fix master/slave ports in Ruby and non-regression scripts
|
ahansson
|
February 13th, 2012, 11:05 a.m.
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[Submitted] mem: Fix memory allocation bug in deferred snoop handling
|
ahansson
|
December 14th, 2015, 10:30 p.m.
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[Submitted] mem: Fix prefetchSquash + memInhibitAsserted bug
|
ahansson
|
February 13th, 2015, 8:36 a.m.
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[Submitted] mem: Fix SenderState related cache deadlock
|
ahansson
|
February 14th, 2013, 6:13 a.m.
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[Submitted] mem: Fix the LPDDR3 page size
|
ahansson
|
October 16th, 2013, 7:50 a.m.
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[Submitted] mem: Fixes for DRAM stats accounting
|
ahansson
|
October 31st, 2013, 9:46 a.m.
|
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[Discarded] MEM: FunctionalPorts are replaced with PortProxys
|
ahansson
|
November 28th, 2011, 10:22 a.m.
|
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[Submitted] mem: Hide WriteInvalidate requests from prefetchers
|
ahansson
|
December 12th, 2014, 5:50 p.m.
|
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[Submitted] mem: Ignore uncacheable MSHRs when finding matches
|
ahansson
|
March 17th, 2015, 7:10 p.m.
|
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[Submitted] mem: Introduce a variable for the retrying port
|
ahansson
|
March 14th, 2013, 7:02 a.m.
|
|
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[Submitted] MEM: Introduce the master/slave port roles in the Python classes
|
ahansson
|
January 18th, 2012, 2:31 a.m.
|
|
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[Submitted] MEM: Introduce the master/slave port sub-classes in C++
|
ahansson
|
March 10th, 2012, 11:54 a.m.
|
|
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|
[Submitted] mem: Just-in-time write scheduling in DRAM controller
|
ahansson
|
October 16th, 2013, 7:45 a.m.
|
|
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[Submitted] mem: Less conservative tRAS in DRAM configurations
|
ahansson
|
October 16th, 2013, 7:43 a.m.
|
|
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[Submitted] mem: Limit the accesses to a page before forcing a precharge
|
ahansson
|
March 7th, 2014, 11:40 p.m.
|
|
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[Submitted] MEM: Make all the port proxy members const
|
ahansson
|
February 24th, 2012, 12:55 a.m.
|
|
|
|
[Submitted] mem: Make cache terminology easier to understand
|
ahansson
|
December 9th, 2015, 11:57 p.m.
|
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[Submitted] mem: Make caches way aware
|
ahansson
|
July 13th, 2015, 4:26 p.m.
|
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[Submitted] mem: Make DRAM read/write switching less conservative
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
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|
[Submitted] mem: Make DRAM write queue draining more aggressive
|
ahansson
|
March 7th, 2014, 11:39 p.m.
|
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|
|
[Submitted] Mem: Make members relating to range and size constant
|
ahansson
|
July 6th, 2012, 6:33 a.m.
|
|
|
|
[Submitted] mem: Make packet bus-related time accounting relative
|
ahansson
|
February 14th, 2013, 1:52 a.m.
|
|
|
|
[Submitted] MEM: Make port proxies use references rather than pointers
|
ahansson
|
February 15th, 2012, 5:56 a.m.
|
|
|
|
[Submitted] mem: Make Request getters const
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] mem: Make returning snoop responses occupy response layer
|
ahansson
|
April 22nd, 2013, 3:37 p.m.
|
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|
[Submitted] Mem: Make SimpleMemory single ported
|
ahansson
|
June 17th, 2012, 10:18 a.m.
|
|
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|
[Submitted] MEM: Make the bus bridge unidirectional and fixed address range
|
ahansson
|
December 23rd, 2011, 1:32 a.m.
|
|
|
|
[Submitted] MEM: Make the bus default port yet another port
|
ahansson
|
December 23rd, 2011, 1:38 a.m.
|
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|
[Submitted] mem: Make the buses multi layered
|
ahansson
|
April 22nd, 2013, 3:35 p.m.
|
|
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[Submitted] mem: Make the coherent crossbar account for timing snoops
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
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|
[Submitted] mem: Make the requests carried by packets const
|
ahansson
|
November 17th, 2014, 6:15 a.m.
|
|
|
|
[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
|
ahansson
|
January 18th, 2012, 2:35 a.m.
|
|
|
|
[Submitted] mem: Make the XBar responsible for tracking response routing
|
ahansson
|
January 5th, 2015, 4:36 p.m.
|
|
|
|
[Submitted] mem: Make tXAW enforcement less conservative and per rank
|
ahansson
|
October 16th, 2013, 7:42 a.m.
|
|
|
|
[Submitted] mem: Merge DRAM latency calculation and bank state update
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
