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Fixed an LSQ full check condition at rename.
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yxw0985
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May 13th, 2011, 2:29 p.m.
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O3: Removed unnecessary unserialize instruction flags.
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yxw0985
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May 13th, 2011, 2:31 p.m.
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ruby: Fixes for RB3139 (move away from Consumer class)
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ymanerka
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October 2nd, 2015, 12:56 a.m.
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Interface to integrate TOPAZ network simulator (http://code.google.com/p/tpzsimul/) within GEM5-RUBY
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vpuente
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March 12th, 2012, 4:37 a.m.
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[se] Initialize Linux' default code and data segments
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vilanova
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September 26th, 2012, 8:34 a.m.
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Provide Python script command line options to set cache latencies
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vilanova
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September 28th, 2012, 8:52 a.m.
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Let the user execute a file just before 'Simulation.run'
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vilanova
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September 28th, 2012, 8:55 a.m.
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O3: Show per-stage aggregate statistics detailing the reasons for block/stall cycles
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vilanova
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October 23rd, 2012, 11:38 a.m.
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imported patch rr_arbiter_fix
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tushar
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February 12th, 2017, 4:36 a.m.
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gpu-compute: Fixed a bug in global memory pipeline
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tqta
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May 18th, 2016, 5:20 p.m.
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gpu-compute: Fixed a bug in decoding Atomic ST
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tqta
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June 13th, 2016, 10:17 p.m.
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CPU: Add functions to get the number of executed instructions and set the
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tmjones
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July 9th, 2010, 6:13 p.m.
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Cache: Provide a function to mark caches as ready from python.
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tmjones
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July 9th, 2010, 6:15 p.m.
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Stats: Allow backing up and restoring of stats which is needed for SMARTS
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tmjones
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July 9th, 2010, 6:21 p.m.
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Sim: Add functionality to the simulation scripts to allow running with
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tmjones
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July 9th, 2010, 6:21 p.m.
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Add Global-Global (gAG) branch predictor
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taylorlloyd
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May 10th, 2013, 10:18 a.m.
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swig: move all swigged objects into m5.internal.swig package
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stever
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September 24th, 2011, 9:51 a.m.
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sim: unify memory & ethernet port binding mechanisms.
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stever
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June 13th, 2013, 7:46 a.m.
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x86: Implementation of Int3 and Int_Ib in long mode
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stever
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August 28th, 2013, 3:52 a.m.
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cache: enable multiple stores per cycle
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stever
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May 14th, 2014, 5:46 a.m.
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o3: issue excl. prefetch as soon as store address is available
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stever
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May 14th, 2014, 5:47 a.m.
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implement remote gdb for x86
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stever
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November 25th, 2014, 6:33 a.m.
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Use x86's Trap flag for remote gdb single-stepping
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stever
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November 25th, 2014, 6:34 a.m.
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mem: implement x86 locked accesses in timing-mode classic cache
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stever
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March 14th, 2015, 5:19 p.m.
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sim: enable adding pid to output directory name
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stever
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August 24th, 2015, 6:55 a.m.
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syscall_emul: create Process output files in output dir
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stever
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August 24th, 2015, 6:56 a.m.
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x86: implement movntps/movntpd SSE insts
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stever
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October 7th, 2015, 3 a.m.
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o3: Fix starvation issue in Round Robin SMT commit policy
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sleimanf
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March 4th, 2014, 10 p.m.
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x86: fixed branching computation for branch uops that only changes nupc and not npc
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sgalan
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January 23rd, 2017, 1:58 p.m.
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commit 70469eba20cdcf091d66cf2ef463318203c7cc71
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rjthakur
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February 21st, 2017, 4:55 p.m.
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arm, kvm: enable running 32-bit Guest under ARM KVM64
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rjthakur
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February 21st, 2017, 5:46 p.m.
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mem: model data array bank in classic cache
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rioshering
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March 31st, 2013, 3:47 p.m.
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mem: add a knob to turn on/off bank blocking model
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rioshering
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April 15th, 2013, 11:54 a.m.
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mem: add retry mechanism for cache fills in classic cache model
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rioshering
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April 17th, 2013, 11:18 a.m.
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cpu: Simplify the rename interface and use RegId
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Rekai
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December 9th, 2016, 6:37 p.m.
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cpu: Result refactoring
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Rekai
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December 9th, 2016, 6:43 p.m.
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cpu: Added interface for vector reg file
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Rekai
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December 9th, 2016, 6:44 p.m.
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arch: ISA parser additions of vector registers
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Rekai
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December 9th, 2016, 6:46 p.m.
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arch: added generic vector register
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Rekai
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December 10th, 2016, 3:38 p.m.
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syscall_emul: implement newfstatat, mbind and faccessat syscall
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puthoorsooraj
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May 5th, 2016, 6:22 p.m.
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configs: add command-line option to enable NoMali in fs.py
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prosenfeld
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January 19th, 2016, 12:10 a.m.
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misc: Add support for switching multiple cores in SystemC
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prosenfeld
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March 4th, 2016, 11:28 p.m.
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Adding TSX support to gem5
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pradip16
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July 5th, 2014, 3:10 a.m.
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cpu, x86: Allow the TLB to be warmed up before CPU switch
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powerjg
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May 20th, 2016, 10:09 p.m.
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sim: Fix fork for multithreaded simulations
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powerjg
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May 20th, 2016, 10:11 p.m.
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Adding some new options to support TRIPS ISA
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pengfeidaxia
|
April 28th, 2010, 5:39 p.m.
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Adding a cpu model named simpleEdgeCPU into M5
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pengfeidaxia
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April 28th, 2010, 5:58 p.m.
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ISA description files for TRIPS ISA
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pengfeidaxia
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April 28th, 2010, 6:29 p.m.
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Make TRIPS binaries available
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pengfeidaxia
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April 28th, 2010, 6:37 p.m.
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sim: eventq: Initialize _curEventQueue to dummy queue
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olajep
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December 28th, 2013, 7:32 p.m.
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