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[Submitted] util: implements "writefile" gem5 op to export file from guest to host filesystem
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ali
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January 9th, 2012, 5:27 p.m.
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[Submitted] sim_cur_ticks: display curTick in stats
|
ali
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December 1st, 2011, 12:29 a.m.
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[Submitted] Bus: Simulation fatals instead of segfault when the destination port is NULL.
|
ali
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December 16th, 2011, 1:32 p.m.
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[Submitted] A more realistic configuration of an ARM-like processor
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rdreslin
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January 11th, 2012, 2:41 p.m.
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[Submitted] Thread: Use inherited baseCpu rather than cpu in SimpleThread
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ahansson
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January 27th, 2012, 5:02 a.m.
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[Submitted] MEM: Remove the otherPort from the cache ports
|
ahansson
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January 18th, 2012, 2:33 a.m.
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swig: move all swigged objects into m5.internal.swig package
|
stever
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September 24th, 2011, 9:51 a.m.
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[Submitted] Regression: Update the regress script after SE/FS merge
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ahansson
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February 1st, 2012, 5:51 a.m.
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[Submitted] Initial patch to make gem5 compile with clang/llvm
|
freedom
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January 10th, 2012, 11:11 p.m.
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[Submitted] Big squashed diff of changes that merge SE and FS modes.
|
gblack
|
December 8th, 2011, 11:04 p.m.
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[Submitted] System: Fix the check which detects running out of physical memory.
|
gblack
|
February 2nd, 2012, 6 p.m.
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[Submitted] Faults: Replace calls to genMachineCheckFault with M5PanicFault.
|
gblack
|
September 24th, 2011, 5 p.m.
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[Submitted] Faults: Turn of arch/faults.hh
|
gblack
|
February 6th, 2012, 4:06 a.m.
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[Submitted] Checker: Access workload element 0 only if there is an element 0.
|
gblack
|
February 5th, 2012, 5:35 a.m.
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[Submitted] m5=>gem5: Make the regression script build gem5.* instead of m5.*
|
gblack
|
February 6th, 2012, 2:20 a.m.
|
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[Discarded] Config: Combine classic and ruby functions for Alpha arch.
|
nilay
|
August 6th, 2011, 12:42 a.m.
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[Discarded] Config: Add ruby_fs.py's functionality to fs.py
|
nilay
|
August 6th, 2011, 12:38 a.m.
|
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[Submitted] MEM: Remove onRetryList from BusPort and rely on retryList
|
ahansson
|
January 18th, 2012, 2:29 a.m.
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[Submitted] O3 CPU: Provide the squashing instruction
|
nilay
|
January 18th, 2012, 10:06 a.m.
|
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[Submitted] O3 CPU: Improve handling of delayed commit flag
|
nilay
|
January 28th, 2012, 9:02 p.m.
|
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[Submitted] O3 CPU: Strengthen condition for handling interrupts
|
nilay
|
January 28th, 2012, 9:01 p.m.
|
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[Submitted] O3 Fetch: Check if PC is pointing to Microcode ROM
|
nilay
|
January 18th, 2012, 9:57 a.m.
|
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[Submitted] MESI: Add queues for stalled requests
|
nilay
|
December 2nd, 2010, 3:58 a.m.
|
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[Submitted] Ruby: Remove isTagPresent() calls from Sequencer.cc
|
nilay
|
December 2nd, 2010, 3:57 a.m.
|
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[Submitted] stats: add separate stats for insts/ops both globally and per cpu model
|
atgutier
|
January 9th, 2012, 1:50 p.m.
|
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[Submitted] mem: Add a requestor ID to each request object.
|
ali
|
February 4th, 2012, 12:24 p.m.
|
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[Submitted] prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
|
ali
|
January 26th, 2012, 4:25 a.m.
|
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[Submitted] mem: fix cache stats to use request ids correctly
|
ali
|
February 4th, 2012, 12:24 p.m.
|
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[Submitted] util/m5/m5.c: in readfile(), added memset to touch all pages - ensure they are in the page table
|
jthestness
|
July 21st, 2010, 2:55 p.m.
|
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[Submitted] M5 utility: remove reserve1_func to build for x86
|
jthestness
|
August 9th, 2010, 10:15 a.m.
|
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SCons: Add an option to dump the build vars, and only do that if asked.
|
gblack
|
March 3rd, 2011, 2:45 a.m.
|
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[Submitted] tests: fix diff-out script for op/inst stat changes.
|
ali
|
February 12th, 2012, 3:47 p.m.
|
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[Submitted] MEM: Introduce the master/slave port roles in the Python classes
|
ahansson
|
January 18th, 2012, 2:31 a.m.
|
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[Submitted] MEM: Pass the ports from Python to C++ using the Swig params
|
ahansson
|
January 18th, 2012, 2:32 a.m.
|
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[Submitted] MEM: Explicit ports and Python binding on CopyEngine
|
ahansson
|
January 18th, 2012, 2:34 a.m.
|
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[Discarded] Regressions: Make the regression diffing script understand host_op_rate.
|
gblack
|
February 12th, 2012, 4:21 p.m.
|
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[Submitted] BP: Fix several Branch Predictor issues.
|
ali
|
August 19th, 2011, 3:19 p.m.
|
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[Submitted] BPred: Fix RAS to handle predicated call/return instructions.
|
ali
|
December 13th, 2011, 10:01 a.m.
|
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[Submitted] Cache warmup: fixed compile errors in Brad's cache warmup patches
|
somayeh
|
April 11th, 2011, noon
|
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[Submitted] my initial implementation of cache flushing
|
somayeh
|
March 6th, 2011, 4:06 p.m.
|
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[Submitted] MEM: Fix master/slave ports in Ruby and non-regression scripts
|
ahansson
|
February 13th, 2012, 11:05 a.m.
|
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[Submitted] Script: Fix the scripts that use the num_cpus cache parameter
|
ahansson
|
February 13th, 2012, 2:38 a.m.
|
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[Submitted] SimObject: make get_config_as_dict() tolerate undefined params
|
stever
|
February 11th, 2012, 12:41 a.m.
|
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[Submitted] MEM: Fatal when no port can be found for an address
|
ahansson
|
February 12th, 2012, 10:22 a.m.
|
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[Submitted] CPU: Round-two unifying instr/data CPU ports across models
|
ahansson
|
February 14th, 2012, 10:34 a.m.
|
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[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
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[Submitted] MEM: Make port proxies use references rather than pointers
|
ahansson
|
February 15th, 2012, 5:56 a.m.
|
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[Submitted] MEM: Move all read/write blob functions from Port to PortProxy
|
ahansson
|
February 15th, 2012, 5:58 a.m.
|
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[Submitted] Ruby: Simplify tester ports by not using SimpleTimingPort
|
ahansson
|
February 16th, 2012, 10:45 a.m.
|
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[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
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