Review Board 2.0.15


All Review Requests

Summary Submitter Posted
Last Updated
mem: Add parameter to reserve MSHR entries for demand access
ahansson
December 12th, 2014, 5:46 p.m.
mem: Rework the structuring of the prefetchers
ahansson
December 12th, 2014, 5:47 p.m.
mem: Fix bug relating to writebacks and prefetches
ahansson
December 12th, 2014, 5:49 p.m.
mem: Fix event scheduling issue for prefetches
ahansson
December 12th, 2014, 5:49 p.m.
mem: Hide WriteInvalidate requests from prefetchers
ahansson
December 12th, 2014, 5:50 p.m.
mem: Change prefetcher to use random_mt
ahansson
December 12th, 2014, 5:50 p.m.
dev: Prevent MC146818 timer RTC events firing before startup
cdirik
November 28th, 2014, 8:57 p.m.
arm: fix build_drive_system when not using default options
atgutier
November 5th, 2014, 9:02 p.m.
minor: fixed LSQ MasterPortID
lukefahr
November 10th, 2014, 5:20 p.m.
x86: add instruction ADDSUBPD
maxime.cscs
November 24th, 2014, 8:27 a.m.
arm: Add unlinkat syscall implementation
mupton
December 3rd, 2014, 7:10 p.m.
mem: Make the XBar responsible for tracking response routing
atgutier
July 7th, 2014, 9:52 p.m.
tests: Fix building the circletest unittest.
gblack
December 17th, 2014, 7:06 a.m.
python: Adding event queue empty check after instantiation before startup
cdirik
December 4th, 2014, 6:45 p.m.
cpuid, x86: Revert "Enabling more features in CPUid"
gblack
December 23rd, 2014, 12:37 a.m.
x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield.
gblack
December 23rd, 2014, 12:38 a.m.
base: Fix assigning between identical bitfields.
gblack
December 17th, 2014, 7:07 a.m.
test: Add a unittest for the BitUnion types.
gblack
December 17th, 2014, 7:08 a.m.
cpu: fix RetiredStores probe point
nnikoleris
January 8th, 2015, 3:13 p.m.
dev: Prevent intel 8254 timer events firing before startup
cdirik
December 4th, 2014, 7:14 p.m.
X86 : fxsave and fxrestore missing template code
castilloe
August 25th, 2014, 2:20 p.m.
syscall emulation: Return correct writev value
jthestness
December 23rd, 2014, 2:51 p.m.
[Discarded] Systemc-GEM5
tito20065
January 20th, 2015, 8:08 a.m.
tests: Remove deprecated InOrderCPU tests
ahansson
December 18th, 2014, 6:46 p.m.
scons: Do not build the InOrderCPU
ahansson
December 19th, 2014, 1:20 p.m.
config, ruby: connect dma to network
musleh
January 20th, 2015, midnight
cpu: commit probe notification on every microop or macroop
nnikoleris
January 14th, 2015, 10:42 a.m.
mem: Clean up Request initialisation
ahansson
January 5th, 2015, 4:35 p.m.
x86: Delay X86 table walk on receiving walker response
ahansson
January 5th, 2015, 4:35 p.m.
mem: Make the XBar responsible for tracking response routing
ahansson
January 5th, 2015, 4:36 p.m.
mem: Always use SenderState for response routing in RubyPort
ahansson
January 5th, 2015, 4:50 p.m.
mem: Remove unused RequestState in the bridge
ahansson
January 5th, 2015, 4:53 p.m.
mem: Remove Packet source from ForwardResponseRecord
ahansson
January 12th, 2015, 4:09 p.m.
mem: Remove unused Packet src and dest fields
ahansson
January 12th, 2015, 4:10 p.m.
x86: kvm: fix the KVM CPU in SE and FS on both Intel and AMD host CPUs
mupton
January 23rd, 2015, 4:52 p.m.
sim: Clean up InstRecord
ali
December 10th, 2014, 5:55 p.m.
cpu: Put all CPU instruction tracers in a single file
ali
December 10th, 2014, 5:54 p.m.
cpu: remove legion tracer
ali
December 10th, 2014, 5:54 p.m.
cpu: Remove all notion that we know when the cpu is misspeculating.
ali
December 10th, 2014, 5:55 p.m.
arm: always set the IsFirstMicroop flag
ali
December 10th, 2014, 5:56 p.m.
[Discarded] mem: Fix race condition in crossbar routing table
powerjg
January 26th, 2015, 8:28 p.m.
config: arm: fix os_flags
musleh
January 13th, 2015, 8:32 p.m.
style: Update the style checker to handle new include order
ahansson
January 26th, 2015, 5:55 p.m.
scons: Avoid implicit command dependencies
ahansson
November 30th, 2014, 9:39 a.m.
config: Adjust DRAM channel interleaving defaults
ahansson
January 21st, 2015, 1:22 p.m.
base: Add XOR-based hashed address interleaving
ahansson
January 21st, 2015, 1:22 p.m.
config: Add XOR hashing to the DRAM channel interleaving
ahansson
January 21st, 2015, 1:23 p.m.
mem: Clarify cache behaviour for pending dirty responses
ahansson
January 26th, 2015, 6:23 p.m.
mem: Clarify express snoop behaviour
ahansson
January 26th, 2015, 6:23 p.m.
cpu: Ensure timing CPU sinks response before sending new request
ahansson
January 27th, 2015, 10:19 a.m.
« < 40 41 42 43 44 45 46 > » 65 pages