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[Submitted] MEM: Do not forward uncacheable to bus snoopers
|
ahansson
|
May 4th, 2012, 9:47 a.m.
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|
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[Submitted] Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
|
ahansson
|
May 3rd, 2012, 11:22 a.m.
|
|
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[Submitted] MEM: Separate requests and responses for timing accesses
|
ahansson
|
April 11th, 2012, 8:23 a.m.
|
|
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[Submitted] Regression: Add a test for x86 timing full system ruby simulation
|
nilay
|
December 30th, 2011, 4:27 p.m.
|
|
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[Submitted] MEM: Use base class Master/SlavePort pointers in the bus
|
ahansson
|
April 9th, 2012, 9:40 a.m.
|
|
|
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[Submitted] MEM: Add the PortId type and a corresponding id field to Port
|
ahansson
|
April 7th, 2012, 9:51 a.m.
|
|
|
|
[Submitted] clang/gcc: Use STL hash function for int64_t and uint64_t
|
ahansson
|
April 18th, 2012, 9:52 p.m.
|
|
|
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[Discarded] SWIG/base: Ensure that ptrdiff_t is available for SWIG by including cstddef.
|
gblack
|
November 27th, 2011, 2:16 a.m.
|
|
|
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[Submitted] X86: Clear out duplicate TLB entries when adding a new one.
|
gblack
|
April 17th, 2012, 5:20 a.m.
|
|
|
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[Submitted] ISA: Put parser generated files in a "generated" directory.
|
gblack
|
April 22nd, 2012, 11:28 p.m.
|
|
|
|
[Submitted] base: Include cassert in trie.hh.
|
gblack
|
April 17th, 2012, 5:20 a.m.
|
|
|
|
[Submitted] X86: Report an error if there's no kernel object, don't blindly use it.
|
gblack
|
April 18th, 2012, 1:55 a.m.
|
|
|
|
[Discarded] tests: Add a unit test for the new AddrTrie data structure.
|
gblack
|
April 8th, 2012, 12:57 a.m.
|
|
|
|
[Submitted] sim: A trie data structure specifically to speed up paging lookups.
|
gblack
|
April 8th, 2012, 12:57 a.m.
|
|
|
|
[Submitted] X86: Use the AddrTrie class to implement the TLB.
|
gblack
|
April 8th, 2012, 12:59 a.m.
|
|
|
|
[Submitted] CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
|
gblack
|
April 15th, 2012, 1:17 a.m.
|
|
|
|
[Discarded] x86: Different microop if all flag bits are written
|
nilay
|
April 12th, 2012, 5:37 p.m.
|
|
|
|
[Submitted] Ruby: Use MasterPort base-class pointers where possible
|
ahansson
|
April 4th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] MEM: Remove the Broadcast destination from the packet
|
ahansson
|
April 4th, 2012, 12:52 a.m.
|
|
|
|
[Submitted] MEM: Separate snoops and normal memory requests/responses
|
ahansson
|
April 2nd, 2012, 6:49 a.m.
|
|
|
|
[Submitted] Regression: Add ANSI colours to highlight test status
|
ahansson
|
April 6th, 2012, 9:16 a.m.
|
|
|
|
[Submitted] clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
|
ahansson
|
April 2nd, 2012, 12:41 p.m.
|
|
|
|
[Submitted] Ruby: Ensure order-dependent iteration uses an ordered map
|
ahansson
|
April 10th, 2012, 10:18 a.m.
|
|
|
|
[Submitted] SPARC: Make PSTATE and HPSTATE a BitUnion.
|
gblack
|
February 4th, 2012, 3:18 a.m.
|
|
|
|
[Submitted] tests: Fix building unit tests.
|
gblack
|
April 8th, 2012, 12:56 a.m.
|
|
|
|
[Submitted] X86: Fix address size handling so real mode works properly.
|
gblack
|
March 16th, 2012, 3:23 a.m.
|
|
|
|
[Submitted] rubytest: seperated read and write ports.
|
beckmann
|
April 4th, 2012, 9:56 p.m.
|
|
|
|
[Submitted] ruby: set SimpleTiming as the default cpu
|
beckmann
|
April 4th, 2012, 10:02 p.m.
|
|
|
|
[Submitted] slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
|
beckmann
|
April 4th, 2012, 10:01 p.m.
|
|
|
|
[Submitted] sim-ruby: checkpointing fixes and dependent eventq improvements
|
beckmann
|
April 4th, 2012, 10:01 p.m.
|
|
|
|
[Submitted] MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality
|
beckmann
|
April 4th, 2012, 9:58 p.m.
|
|
|
|
[Submitted] MOESI_hammer: tbe allocation and dependent wakeup fixes
|
beckmann
|
April 4th, 2012, 10 p.m.
|
|
|
|
[Submitted] python: added __nonzero__ function to SimObject Bool params
|
beckmann
|
April 4th, 2012, 9:59 p.m.
|
|
|
|
[Discarded] request: added split Paddr function
|
beckmann
|
April 4th, 2012, 9:58 p.m.
|
|
|
|
[Submitted] MEM: Enable multiple distributed generalized memories
|
ahansson
|
March 21st, 2012, 4:20 p.m.
|
|
|
|
[Submitted] Ruby X86: problem in setting DMA port, related to the changeset 8850
|
nilay
|
March 14th, 2012, 8:53 p.m.
|
|
|
|
[Discarded] Config: Partially roll back changeset 8920
|
nilay
|
April 3rd, 2012, 9:43 p.m.
|
|
|
|
[Submitted] Python: Make the All proxy traverse SimObject children as well
|
ahansson
|
March 21st, 2012, 10:07 a.m.
|
|
|
|
[Submitted] Ruby: Fix the example configurations option parsing
|
ahansson
|
April 4th, 2012, 3:44 p.m.
|
|
|
|
[Submitted] Atomic: Remove the physmem_port and access memory directly
|
ahansson
|
March 20th, 2012, 10:30 a.m.
|
|
|
|
[Submitted] MEM: Remove legacy DRAM in preparation for memory updates
|
ahansson
|
March 21st, 2012, 10:04 a.m.
|
|
|
|
[Submitted] Ruby: Remove the physMemPort and instead access memory directly
|
ahansson
|
March 20th, 2012, 8:31 a.m.
|
|
|
|
[Submitted] MEM: Introduce the master/slave port sub-classes in C++
|
ahansson
|
March 10th, 2012, 11:54 a.m.
|
|
|
|
[Submitted] CPU: Unify initMemProxies across CPUs and simulation modes
|
ahansson
|
March 27th, 2012, 3:55 a.m.
|
|
|
|
[Submitted] Config: Change the way options are added
|
nilay
|
March 24th, 2012, 1:30 p.m.
|
|
|
|
[Submitted] Config: Move setWorkCountOptions() to Simulation.py
|
nilay
|
March 24th, 2012, 1:17 p.m.
|
|
|
|
[Submitted] range_map: Enable const find and iteration
|
ahansson
|
March 21st, 2012, 10:06 a.m.
|
|
|
|
[Submitted] Power: Change bitfield name to avoid conflicts with range_map
|
ahansson
|
March 21st, 2012, 10:03 a.m.
|
|
|
|
[Discarded] Extend physical memory beyond 4GB
|
nilay
|
February 15th, 2012, 3:06 p.m.
|
|
|
|
[Submitted] MEM: Unify bus access methods and prepare for master/slave split
|
ahansson
|
February 29th, 2012, 3:06 a.m.
|
|
