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[Submitted] cpu: add more instruction mix statistics
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ahansson
|
April 23rd, 2014, 12:21 p.m.
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[Submitted] dev, pci: Implement basic VirtIO support
|
ahansson
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September 10th, 2014, 7:51 a.m.
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[Submitted] o3: Use shared_ptr for MemDepEntry
|
ahansson
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September 29th, 2014, 10:40 a.m.
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[Submitted] mem: Clean up Request initialisation
|
ahansson
|
January 5th, 2015, 4:35 p.m.
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[Submitted] sim: Move the BaseTLB to src/arch/generic/
|
ahansson
|
February 5th, 2015, 10:59 a.m.
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[Submitted] mem: Add option to force in-order insertion in PacketQueue
|
ahansson
|
February 19th, 2015, 7:56 a.m.
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[Submitted] mem: Modernise MSHR iterators to C++11
|
ahansson
|
March 17th, 2015, 7:09 p.m.
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[Discarded] MEM: FunctionalPorts are replaced with PortProxys
|
ahansson
|
November 28th, 2011, 10:22 a.m.
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[Submitted] MEM: Make the bus default port yet another port
|
ahansson
|
December 23rd, 2011, 1:38 a.m.
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[Submitted] Ruby: Remove the physMemPort and instead access memory directly
|
ahansson
|
March 20th, 2012, 8:31 a.m.
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[Submitted] mem: Do not include snoop-filter latency in crossbar occupancy
|
ahansson
|
August 19th, 2015, 9:06 a.m.
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[Submitted] Bus: Turn the PortId into a transport function parameter
|
ahansson
|
May 23rd, 2012, 6:34 a.m.
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[Submitted] Port: Make getAddrRanges const
|
ahansson
|
June 6th, 2012, 9:45 a.m.
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[Discarded] mem: Align rules for sinking packets at the slave
|
ahansson
|
October 26th, 2015, 6:14 p.m.
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[Submitted] config: Use SimpleDRAM in full-system, and with o3 and inorder
|
ahansson
|
October 20th, 2012, 8:44 a.m.
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[Submitted] mem: Add tTAW and tFAW to the SimpleDRAM model
|
ahansson
|
December 6th, 2012, 8:28 p.m.
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[Submitted] util: Add a utility script for decoding packet traces
|
ahansson
|
March 14th, 2013, 7:06 a.m.
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[Submitted] mem: Align cache timing to clock edges
|
ahansson
|
June 4th, 2013, 10:46 a.m.
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[Submitted] mem: Use STL deque in favour of list for DRAM queues
|
ahansson
|
July 18th, 2013, 12:59 p.m.
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[Submitted] mem: Fix bug in PhysicalMemory use of mmap and munmap
|
ahansson
|
February 13th, 2014, 2:41 p.m.
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[Submitted] mem: Make DRAM write queue draining more aggressive
|
ahansson
|
March 7th, 2014, 11:39 p.m.
|
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[Submitted] sim, arm: implement more of the at variety syscalls
|
ahansson
|
April 23rd, 2014, 12:26 p.m.
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[Submitted] base: Replace the internal varargs stuff with C++11 constructs
|
ahansson
|
August 13th, 2014, 12:51 p.m.
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|
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[Submitted] arch: Cleanup unused ISA traits constants
|
ahansson
|
August 22nd, 2014, 8:17 a.m.
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|
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[Submitted] mem: Add a simple snoop counter per bus
|
ahansson
|
September 10th, 2014, 7:53 a.m.
|
|
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[Submitted] scons: Generate a single debug flag C++ file
|
ahansson
|
September 29th, 2014, 10:37 a.m.
|
|
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[Submitted] cpu: Move packet deallocation to recvTimingResp in the O3 CPU
|
ahansson
|
November 17th, 2014, 6:18 a.m.
|
|
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[Submitted] scons: Ensure dictionary iteration is sorted by key
|
ahansson
|
November 25th, 2014, 9:49 a.m.
|
|
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[Submitted] mem: Add stack distance statistics to the CommMonitor
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
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[Submitted] config: Adjust DRAM channel interleaving defaults
|
ahansson
|
January 21st, 2015, 1:22 p.m.
|
|
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|
[Submitted] arm, dev: Add a UFS device
|
ahansson
|
March 27th, 2015, 1:57 p.m.
|
|
|
|
[Submitted] MEM: Explicit ports and Python binding on CopyEngine
|
ahansson
|
January 18th, 2012, 2:34 a.m.
|
|
|
|
[Submitted] CPU: Round-two unifying instr/data CPU ports across models
|
ahansson
|
February 14th, 2012, 10:34 a.m.
|
|
|
|
[Submitted] scons: Add LIBRARY_PATH from the user environment to Scons
|
ahansson
|
July 11th, 2012, 4 a.m.
|
|
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[Submitted] mem: Deduce if cache should forward snoops
|
ahansson
|
December 28th, 2015, 6:14 p.m.
|
|
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|
[Submitted] Inet: Remove the SackRange and its use
|
ahansson
|
August 29th, 2012, 11:53 a.m.
|
|
|
|
[Submitted] Mem: Separate the host and guest views of memory backing store
|
ahansson
|
September 11th, 2012, 11:20 a.m.
|
|
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[Submitted] scons: Enable building with the gcc/clang Address Sanitizer
|
ahansson
|
February 15th, 2016, 9 a.m.
|
|
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|
[Submitted] Mem: Use cycles to express cache-related latencies
|
ahansson
|
September 28th, 2012, 7 a.m.
|
|
|
|
stats: Add SQLite database as an output format
|
ahansson
|
January 15th, 2013, 10:26 a.m.
|
|
|
|
[Submitted] scons: Add warning for overloaded virtual functions
|
ahansson
|
February 14th, 2013, 1:54 a.m.
|
|
|
|
[Submitted] mem: Add a LPDDR3-1600 configuration
|
ahansson
|
April 22nd, 2013, 2:45 p.m.
|
|
|
|
[Submitted] cpu: Fix timing CPU drain check
|
ahansson
|
August 18th, 2013, 3:35 p.m.
|
|
|
|
[Submitted] dev: Set HDLCD default pixel clock for 1080p @ 60Hz
|
ahansson
|
April 23rd, 2014, 12:18 p.m.
|
|
|
|
[Submitted] mem: Add DRAM cycle time
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
|
|
|
[Submitted] mem: Remove the GHB prefetcher from the source tree
|
ahansson
|
September 10th, 2014, 7:51 a.m.
|
|
|
|
[Submitted] arch,x86,mem: Dynamically determine the ISA for Ruby store check
|
ahansson
|
September 29th, 2014, 10:39 a.m.
|
|
|
|
[Submitted] mem: Use the range cache for lookup as well as access
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] cpu: Add a PC-value to the traffic generator requests
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] mem: Avoid DRAM write queue iteration for merging and read lookup
|
ahansson
|
April 24th, 2015, 4:32 p.m.
|
|
