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[Submitted] mem: Cancel cache retry event when blocking port
|
ahansson
|
March 14th, 2013, 7:04 a.m.
|
|
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[Submitted] mem: Change AbstractMemory defaults to match the common case
|
ahansson
|
July 19th, 2013, 8:33 a.m.
|
|
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|
[Submitted] mem: Change accessor function names to match the port interface
|
ahansson
|
February 14th, 2013, 1:53 a.m.
|
|
|
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[Submitted] mem: Change memory defaults to be more representative
|
ahansson
|
March 7th, 2014, 11:45 p.m.
|
|
|
|
[Submitted] mem: Change prefetcher to use random_mt
|
ahansson
|
December 12th, 2014, 5:50 p.m.
|
|
|
|
[Discarded] MEM: Changes for SETranslatingProxy integration into Ruby
|
ahansson
|
November 28th, 2011, 10:19 a.m.
|
|
|
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[Submitted] mem: Clarification of packet crossbar timings
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
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[Submitted] mem: Clarify cache behaviour for pending dirty responses
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
|
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[Submitted] mem: Clarify cache MSHR handling on fill
|
ahansson
|
October 13th, 2015, 3:35 p.m.
|
|
|
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[Submitted] mem: Clarify express snoop behaviour
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
|
|
|
[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
|
[Submitted] mem: Clean up packet data allocation
|
ahansson
|
November 17th, 2014, 6:17 a.m.
|
|
|
|
[Submitted] mem: Clean up Request initialisation
|
ahansson
|
January 5th, 2015, 4:35 p.m.
|
|
|
|
[Submitted] MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
|
ahansson
|
January 29th, 2012, 10:49 a.m.
|
|
|
|
[Submitted] mem: Cleanup flow for uncacheable accesses
|
ahansson
|
March 17th, 2015, 7:10 p.m.
|
|
|
|
[Discarded] mem: Cleanup packet attributes and rely on command type
|
ahansson
|
August 6th, 2015, 9:41 p.m.
|
|
|
|
[Submitted] mem: Cleanup Packet::checkFunctional and hasData usage
|
ahansson
|
November 17th, 2014, 6:16 a.m.
|
|
|
|
[Submitted] mem: Convert Request static const flags to enums
|
ahansson
|
June 26th, 2015, 9:26 p.m.
|
|
|
|
[Submitted] mem: Create a request copy for deferred snoops
|
ahansson
|
April 2nd, 2015, 9:31 a.m.
|
|
|
|
[Submitted] mem: Create a separate class for the cache write buffer
|
ahansson
|
February 24th, 2016, 9:28 a.m.
|
|
|
|
[Submitted] mem: Cycles converted to Ticks in atomic cache accesses
|
ahansson
|
May 23rd, 2013, 12:47 a.m.
|
|
|
|
[Submitted] mem: DDR3 config for comparing with DRAMSim2
|
ahansson
|
March 7th, 2014, 11:36 p.m.
|
|
|
|
[Submitted] mem: Deallocate all write-queue entries when sent
|
ahansson
|
April 20th, 2016, 5:18 p.m.
|
|
|
|
[Submitted] mem: Deduce if cache should forward snoops
|
ahansson
|
December 28th, 2015, 6:14 p.m.
|
|
|
|
[Submitted] mem: Delay responses in the crossbar before forwarding
|
ahansson
|
June 15th, 2015, 6:06 p.m.
|
|
|
|
[Submitted] Mem: Determine bus block size during initialisation
|
ahansson
|
September 21st, 2012, 9:03 a.m.
|
|
|
|
[Submitted] MEM: Differentiate functional cache accesses from CPU and memory
|
ahansson
|
January 5th, 2012, 5:17 a.m.
|
|
|
|
[Submitted] mem: Do not allocate space for packet data if not needed
|
ahansson
|
December 16th, 2015, 12:40 a.m.
|
|
|
|
[Submitted] mem: Do not alter cache block state on uncacheable snoops
|
ahansson
|
December 9th, 2015, 11:57 p.m.
|
|
|
|
[Submitted] MEM: Do not forward uncacheable to bus snoopers
|
ahansson
|
May 4th, 2012, 9:47 a.m.
|
|
|
|
[Submitted] mem: Do not include snoop-filter latency in crossbar occupancy
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] mem: Do not rely on the NeedsWritable flag for responses
|
ahansson
|
December 29th, 2015, 4:16 p.m.
|
|
|
|
[Submitted] mem: Do not treat CleanEvict as a write operation
|
ahansson
|
October 30th, 2015, 10:33 a.m.
|
|
|
|
[Submitted] mem: Do not use sender state to track forwarded snoops in cache
|
ahansson
|
December 9th, 2015, 11:51 p.m.
|
|
|
|
[Submitted] mem: Downstream components consumes new crossbar delays
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] mem: DRAM controller tidying up
|
ahansson
|
March 7th, 2014, 11:43 p.m.
|
|
|
|
[Submitted] mem: DRAMPower integration for on-line DRAM power stats
|
ahansson
|
September 29th, 2014, 10:44 a.m.
|
|
|
|
[Submitted] mem: DRAMPower trace formatting script
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
|
|
|
[Submitted] mem: DRAMPower trace output
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
|
|
|
[Submitted] mem: Dynamically determine page bytes in memory components
|
ahansson
|
September 29th, 2014, 10:39 a.m.
|
|
|
|
[Submitted] mem: Edit proto Packet and enhance the python script
|
ahansson
|
February 21st, 2014, 1:30 p.m.
|
|
|
|
[Submitted] MEM: Enable multiple distributed generalized memories
|
ahansson
|
March 21st, 2012, 4:20 p.m.
|
|
|
|
[Submitted] mem: Enforce insertion order on the cache response path
|
ahansson
|
October 13th, 2015, 3:36 p.m.
|
|
|
|
[Submitted] mem: Enforce strict use of busFirst- and busLastWordTime
|
ahansson
|
February 14th, 2013, 1:53 a.m.
|
|
|
|
[Submitted] mem: Ensure DRAM controller is idle when in atomic mode
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Ensure DRAM refresh respects timings
|
ahansson
|
April 23rd, 2014, 12:33 p.m.
|
|
|
|
[Submitted] MEM: Explicit ports and Python binding on CopyEngine
|
ahansson
|
January 18th, 2012, 2:34 a.m.
|
|
|
|
[Submitted] mem: Explicitly check MSHR snoops for cases not dealt with
|
ahansson
|
December 9th, 2015, 11:54 p.m.
|
|
|
|
[Submitted] MEM: Fatal when no port can be found for an address
|
ahansson
|
February 12th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] mem: Filter cache snoops based on address ranges
|
ahansson
|
January 23rd, 2014, 8:23 a.m.
|
|
