Review Board 2.0.15


All Review Requests

Summary
Submitter Posted Last Updated
cache: Fix handling of LL/SC requests under contention
ali
June 12th, 2014, 10:46 p.m.
cache: Fix issue where IO cache read, prefetch and dirty data in L1 cause coherence bug.
ali
March 26th, 2013, 1:54 p.m.
Cache: Fix the LRU policy for classic memory hierarchy
lena
June 18th, 2012, 4:14 p.m.
Cache: fix vector stats in classic cache to have matching lengths
hsul
April 22nd, 2011, 5:13 p.m.
Cache: Panic if you attempt to create a checkpoint with a cache in the system
ali
May 2nd, 2012, 1:07 p.m.
[Discarded] cache: properly initialize vector stats that are per context
nate
April 19th, 2011, 6:56 p.m.
Cache: Provide a function to mark caches as ready from python.
tmjones
July 9th, 2010, 6:15 p.m.
Cache: Remove dangling doWriteback declaration
ahansson
May 23rd, 2012, 6:30 a.m.
cache: remove drainManager because it's not used
atgutier
October 16th, 2012, 9:47 a.m.
[Discarded] Cache: Remove redundant check for uncacheable snoops
ahansson
May 18th, 2012, 9:12 a.m.
cache: remove redundant test in recvTimingResp()
stever
February 9th, 2015, 6:05 a.m.
Cache: Split invalidateBlk up to seperate block vs. tags
lena
July 5th, 2012, 5:58 p.m.
CacheMemory: add allocateVoid() that is == allocate() but no return value.
hsul
March 31st, 2011, 12:19 p.m.
Change interface between coherence protocols and CacheMemory
nilay
December 21st, 2010, 9:18 a.m.
[Discarded] Changes to the gem5 memory-system (release-0.1)
ahansson
July 15th, 2011, 9:03 a.m.
[Discarded] Changes to the gem5 memory-system (release-0.2)
ahansson
August 5th, 2011, 10:13 a.m.
Checker CPU: change the floating reg index in the copyResult function
npremill
February 6th, 2013, 5:38 a.m.
checker cpu: make checker cpu id match its host's cpu id
atgutier
July 19th, 2012, 2:30 p.m.
Checker: Access workload element 0 only if there is an element 0.
gblack
February 5th, 2012, 5:35 a.m.
Checker: Bump the realview-o3-checker regression
ahansson
August 25th, 2012, 4 a.m.
Checker: Fix checker CPU ports
ahansson
August 25th, 2012, 4 a.m.
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
blakegw
February 8th, 2012, 7:41 a.m.
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
blakegw
February 8th, 2012, 7:40 a.m.
CheckerCPU: Make some basic regression tests for CheckerCPU
blakegw
February 8th, 2012, 7:41 a.m.
CheckerCPU: Re-factor CheckerCPU to be compatible current state of gem5
ali
November 3rd, 2011, 1:27 p.m.
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
blakegw
November 23rd, 2011, 2:50 p.m.
Checkpoint: Fix broken checkpointing functionality
ahansson
August 20th, 2012, 7:04 a.m.
Checkpoint: Make system serialize call children
ahansson
October 12th, 2012, 1:46 a.m.
[Discarded] checkpoint: move curTick from globals to eventq
nilay
January 24th, 2013, 12:08 p.m.
Checkpoint: Pass maxtick to avoid undefined variable
ahansson
September 11th, 2012, 9:19 a.m.
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
ahansson
April 2nd, 2012, 12:41 p.m.
clang/gcc: Use STL hash function for int64_t and uint64_t
ahansson
April 18th, 2012, 9:52 p.m.
clang: Fix issues identified by the clang static analyzer
ahansson
September 11th, 2012, 3:41 a.m.
clang: Fix recently introduced clang compilation errors
ahansson
March 6th, 2012, 9:19 a.m.
CLCD: Fix some serialization bugs with the clcd controller.
ali
February 11th, 2011, 4:37 p.m.
Clock: Add a Cycles wrapper class and use where applicable
ahansson
August 3rd, 2012, 5:56 a.m.
Clock: Inherit the clock from parent by default
ahansson
September 21st, 2012, 9:06 a.m.
Clock: Make Tick unsigned and remove UTick
ahansson
July 26th, 2012, 4:55 a.m.
Clock: Move the clock and related functions to ClockedObject
ahansson
July 11th, 2012, 1:56 a.m.
Clock: Rework clocks to avoid tick-to-cycle transformations
ahansson
July 26th, 2012, 5 a.m.
commit 70469eba20cdcf091d66cf2ef463318203c7cc71
rjthakur
February 21st, 2017, 4:55 p.m.
commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
rjthakur
November 16th, 2016, 11:02 p.m.
commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
rjthakur
November 21st, 2016, 7:03 p.m.
Compile gem5 on systems where python2 and python3 co-exists
hvatum
March 11th, 2014, 10:08 a.m.
Compiler: Add an M5_NO_INLINE define.
gblack
November 27th, 2011, 2:15 a.m.
config, cpu: fix progress interval for switched CPUs" progress_interval_config.diff
musleh
April 2nd, 2015, 10:56 p.m.
config, kvm: Enabling KvmCPU in SE mode
alexdutu
August 1st, 2014, 3:53 p.m.
config, mem: add command-line options for L2 MSHR queue size and hit latency
cataldo
June 3rd, 2016, 9:03 p.m.
config, mem: new L2 cache architectures for the classic memory system
cataldo
June 17th, 2016, 3:03 p.m.
config, ruby: connect dma to network
musleh
January 20th, 2015, midnight
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