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[Submitted] misc: fix includes in util/systemc
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cmenard
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February 5th, 2017, 2:05 p.m.
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[Submitted] misc: Implement the Base SystemC Module as an sc_channel.
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cmenard
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January 9th, 2017, 12:17 p.m.
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[Discarded] util/m5: use CURDIR instead of PWD
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cirosantilli
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February 21st, 2018, 4:56 p.m.
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[Submitted] x86: Implementation of Int3 and Int_Ib in long mode
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chrism
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June 28th, 2013, 1:25 p.m.
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[Submitted] x86: bugfix: lret instruction has to increment the stack pointer
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chrism
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April 17th, 2013, 4:37 a.m.
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[Submitted] arm: enable EL2 support
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cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] sim: Adding thermal model support
|
cdunham
|
March 5th, 2016, 12:21 a.m.
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[Submitted] sim: make warning for absent optional parameters optional
|
cdunham
|
June 30th, 2015, 12:35 a.m.
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[Submitted] cpu,isa,mem: Adds per-thread wakeup logic
|
cdunham
|
July 30th, 2015, 6:47 p.m.
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[Discarded] cpu: remove O3's fetch address validity check
|
cdunham
|
October 12th, 2015, 4:13 p.m.
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[Submitted] cpu: Fix BTB threading oversight
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] mem: Sort memory commands and update DRAMPower
|
cdunham
|
August 4th, 2016, 4:35 p.m.
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[Discarded] multi-gem5: Fix draining and serialization
|
cdunham
|
September 21st, 2015, 6:59 p.m.
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[Submitted] ext: Add SST connector
|
cdunham
|
February 20th, 2015, 6:47 p.m.
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[Submitted] sim, arm: add checkpoint upgrader for d02b45a5
|
cdunham
|
May 27th, 2015, 10:18 p.m.
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[Submitted] cpu: Add TraceCPU to playback elastic traces
|
cdunham
|
August 11th, 2015, 9:05 p.m.
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[Submitted] util: update Java JNI interface to m5ops
|
cdunham
|
February 13th, 2016, 12:33 a.m.
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[Submitted] cpu: Fix Minor SMT WFI/drain interaction issues
|
cdunham
|
July 5th, 2016, 2 p.m.
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[Submitted] arm: warn not fail on use of missing miscreg CNTHCTL_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: correctly assign faulting IPA's to HPFAR_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] sim: Thermal support for Linux
|
cdunham
|
March 5th, 2016, 12:21 a.m.
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[Submitted] mem: Update DRAM configuration names
|
cdunham
|
January 17th, 2017, 10:04 p.m.
|
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[Submitted] sim: support checkpointing std::set<std::string>'s
|
cdunham
|
June 30th, 2015, 12:35 a.m.
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[Submitted] arm: Change TLB software caching
|
cdunham
|
July 30th, 2015, 6:47 p.m.
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[Submitted] mem: Remove threadId from memory request class
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
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[Submitted] base: Add total() to Vector2D stat
|
cdunham
|
May 31st, 2016, 10:43 a.m.
|
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[Submitted] mem: Modify drain to ensure banks and power are idled
|
cdunham
|
August 4th, 2016, 4:35 p.m.
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[Submitted] dist, dev: fix etherswitch upgrade script
|
cdunham
|
December 15th, 2016, 4:50 p.m.
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[Submitted] arm: Fix trapping to Hypervisor during MSR/MRS read/write
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: add stage2 translation support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Discarded] multi-gem5: Fix packet ordering
|
cdunham
|
September 21st, 2015, 6:59 p.m.
|
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[Submitted] config: Support full-system with SST's memory system
|
cdunham
|
February 20th, 2015, 6:47 p.m.
|
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[Submitted] cpu: Change thread assignents for heterogenous SMT
|
cdunham
|
July 30th, 2015, 6:46 p.m.
|
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[Submitted] util: Add decode and encode scripts for elastic traces
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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[Submitted] cpu: Enforce 1 interrupt controller per thread
|
cdunham
|
October 5th, 2015, 6:52 p.m.
|
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[Submitted] pseudo inst,util: Add an optional key parameter for the initparam pseudo instruction
|
cdunham
|
November 19th, 2015, 5:44 p.m.
|
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[Submitted] multi-gem5: Add checkpoint support for multi gem5 runs
|
cdunham
|
June 1st, 2015, 8:05 p.m.
|
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[Submitted] arm: Add AArch64 hypervisor call instruction 'hvc'
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: refactor page table walking
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Check TLB stage 2 permissions in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] pwr: Add power states to ClockedObject
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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cpu: Add a SynchroTrace replay model
|
cdunham
|
October 26th, 2016, 11:04 p.m.
|
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[Submitted] sim,kvm,arm: fix typos
|
cdunham
|
January 17th, 2017, 10:04 p.m.
|
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[Submitted] sim: tag-based checkpoint versioning
|
cdunham
|
June 30th, 2015, 12:35 a.m.
|
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[Submitted] base: remove Trace::enabled flag
|
cdunham
|
August 31st, 2015, 6:35 p.m.
|
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[Submitted] cpu: Add instruction opclass histogram to minor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
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[Submitted] mem: Add snoop traffic statistic
|
cdunham
|
May 31st, 2016, 10:43 a.m.
|
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[Submitted] mem: Add callback to compute stats prior to dump event
|
cdunham
|
August 4th, 2016, 4:35 p.m.
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