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[Submitted] base: Encapsulate the underlying fields in AddrRange
|
ahansson
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October 30th, 2012, 8:57 a.m.
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stats: Add documentation to the python statistics system
|
ahansson
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January 15th, 2013, 10:24 a.m.
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[Submitted] scons: Fix up numerous warnings about name shadowing
|
ahansson
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February 14th, 2013, 1:53 a.m.
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[Submitted] config: Make configs/common a Python package
|
ahansson
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October 13th, 2016, 2:10 p.m.
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[Submitted] mem: Avoid explicitly zeroing the memory backing store
|
ahansson
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April 22nd, 2013, 2:44 p.m.
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[Submitted] mem: Spring cleaning of MSHR and MSHRQueue
|
ahansson
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May 9th, 2013, 3:18 a.m.
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[Submitted] arm: Add Makefile for aarch64 build of util/m5
|
ahansson
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April 23rd, 2014, 12:15 p.m.
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[Submitted] mem: Add precharge all (PREA) to the DRAM controller
|
ahansson
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April 23rd, 2014, 12:36 p.m.
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[Submitted] mem: write streaming support via WriteInvalidate promotion
|
ahansson
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August 13th, 2014, 2:08 p.m.
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[Submitted] config: Cleanup .json config file generation
|
ahansson
|
September 10th, 2014, 7:50 a.m.
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[Submitted] arm: Add helper methods to setup architected PMU events
|
ahansson
|
September 29th, 2014, 10:39 a.m.
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[Submitted] cpu: Ensure timing CPU sinks response before sending new request
|
ahansson
|
January 27th, 2015, 10:19 a.m.
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[Submitted] mem, cpu: Add a separate flag for strictly ordered memory
|
ahansson
|
March 30th, 2015, 9:17 a.m.
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[Submitted] MEM: Simplify ports by removing EventManager
|
ahansson
|
December 19th, 2011, 5:55 a.m.
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[Submitted] mem: Add snoop filters to L2 crossbars, and check size
|
ahansson
|
August 21st, 2015, 3:49 p.m.
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[Submitted] Config: Exit with fatal if a port is already connected
|
ahansson
|
May 18th, 2012, 9:10 a.m.
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[Submitted] mem: Add an option to perform clean writebacks from caches
|
ahansson
|
October 19th, 2015, 5:02 p.m.
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[Submitted] Packet: Remove NACKs from packet and its use in endpoints
|
ahansson
|
July 21st, 2012, 5:11 a.m.
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[Submitted] mem: Move the point of coherency to the coherent crossbar
|
ahansson
|
January 1st, 2016, 2:33 p.m.
|
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[Submitted] AddrRange: Transition from Range<T> to AddrRange
|
ahansson
|
September 3rd, 2012, 9:22 p.m.
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[Submitted] mem: Adjust cache queue reserve to more conservative values
|
ahansson
|
February 24th, 2016, 9:28 a.m.
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[Submitted] mem: Remove the joining of neighbouring ranges
|
ahansson
|
December 6th, 2012, 8:01 p.m.
|
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[Submitted] scons: Allow pkg-config to fail and continue
|
ahansson
|
January 8th, 2013, 6:47 a.m.
|
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[Submitted] mem: Add support for multi-channel DRAM configurations
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
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[Submitted] cpu: Remove CpuPort and use MasterPort in the CPU classes
|
ahansson
|
March 14th, 2013, 7 a.m.
|
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[Submitted] sim: Make MaxTick in Python match the one in C++
|
ahansson
|
July 12th, 2013, 9:41 a.m.
|
|
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[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (2/2)
|
ahansson
|
August 19th, 2013, 9:41 a.m.
|
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[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
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[Discarded] arch: support dynamic ISA file generation in SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
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[Submitted] config: Add options to take/resume from SimPoint checkpoints
|
ahansson
|
November 20th, 2014, 9:43 a.m.
|
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[Submitted] arch, cpu: Factor out the ExecContext into a proper base class
|
ahansson
|
August 19th, 2014, 9:28 a.m.
|
|
|
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[Submitted] mem: Add memory rank-to-rank delay
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
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[Submitted] mem: Add missig timing and current parameters to DRAM configs
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
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[Submitted] mem: Remove redundant Packet::allocate calls
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
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[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
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[Submitted] cpu: Fix a bug in counting issued instructions in MinorCPU
|
ahansson
|
May 8th, 2015, 1:11 p.m.
|
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[Submitted] mem: Allow read-only caches and check compliance
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
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[Submitted] mem: Transition away from isSupplyExclusive for writebacks
|
ahansson
|
July 13th, 2015, 3:16 p.m.
|
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[Submitted] Python: Make the All proxy traverse SimObject children as well
|
ahansson
|
March 21st, 2012, 10:07 a.m.
|
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[Submitted] Bus: Remove redundant packet parameter from isOccupied
|
ahansson
|
May 25th, 2012, 9:47 a.m.
|
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[Submitted] mem: Remove unused cache squash functionality
|
ahansson
|
December 9th, 2015, 11:52 p.m.
|
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[Submitted] Checker: Fix checker CPU ports
|
ahansson
|
August 25th, 2012, 4 a.m.
|
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[Submitted] Ruby: Bump the stats after recent memory controller changes
|
ahansson
|
September 10th, 2012, 8:49 a.m.
|
|
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[Submitted] config: Remove unused mem_size in fs.py
|
ahansson
|
October 25th, 2012, 10:35 a.m.
|
|
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[Submitted] sim: Make clock private and access using clockPeriod()
|
ahansson
|
February 14th, 2013, 1:52 a.m.
|
|
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[Submitted] tests: Prune 00.gzip from the regressions
|
ahansson
|
June 6th, 2013, 2:28 p.m.
|
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[Submitted] mem: Change memory defaults to be more representative
|
ahansson
|
March 7th, 2014, 11:45 p.m.
|
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[Submitted] scons: update SCons SWIG version check to 2.0.4
|
ahansson
|
April 23rd, 2014, 12:10 p.m.
|
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[Submitted] mem: Add DRAM power states to the controller
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
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[Submitted] tests: Use O3_ARM_v7a config for full-system ARM regressions
|
ahansson
|
August 13th, 2014, 2:07 p.m.
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