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[Submitted] config,cpu: Add SMT support to Atomic and Timing CPUs
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cdunham
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July 30th, 2015, 6:47 p.m.
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[Submitted] base: support gzip-compressed object files
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cdunham
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September 21st, 2015, 11:42 p.m.
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[Submitted] base: remove Trace::enabled flag
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cdunham
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August 31st, 2015, 6:35 p.m.
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[Submitted] base: Add total() to Vector2D stat
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cdunham
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May 31st, 2016, 10:43 a.m.
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[Submitted] arm: warn not fail on use of missing miscreg CNTHCTL_EL2
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cdunham
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June 21st, 2016, 1:41 p.m.
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[Submitted] arm: tweak MPIDR setting when using SMT
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cdunham
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July 30th, 2015, 6:47 p.m.
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[Submitted] arm: Squash after returning from exceptions in v7
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cdunham
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February 10th, 2016, 12:04 a.m.
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[Submitted] arm: s/ctx_id/ctx/ the GIC
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cdunham
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July 18th, 2016, 3:26 p.m.
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[Submitted] arm: refactor page table walking
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cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
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cdunham
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June 21st, 2016, 1:41 p.m.
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[Submitted] arm: invalidate TLB miscreg cache on modification of HSCTLR
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cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix trapping to Hypervisor during MSR/MRS read/write
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix stage 2 memory attribute checking in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix stage 2 determination in table walker
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix secure state checking in various places
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix EL perceived at TLB for address translation instructions
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: enable EL2 support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: correctly assign faulting IPA's to HPFAR_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Check TLB stage 2 permissions in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Change TLB software caching
|
cdunham
|
July 30th, 2015, 6:47 p.m.
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[Submitted] arm: change instruction classes to catch hyp traps
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: bank GIC registers per CPU
|
cdunham
|
July 18th, 2016, 3:26 p.m.
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[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: add stage2 translation support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Add check to fault routing for hypervisor/virtualization
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Add AArch64 hypervisor call instruction 'hvc'
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm, kvm: remove KvmGic
|
cdunham
|
January 17th, 2017, 10:04 p.m.
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[Submitted] arm, kvm: implement MuxingKvmGic
|
cdunham
|
January 17th, 2017, 10:04 p.m.
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[Submitted] arm, kvm: Automatically use the MuxingKvmGic
|
cdunham
|
January 17th, 2017, 10:04 p.m.
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[Discarded] arm, config: Fixups for the example big.LITTLE(tm) configuration
|
cdunham
|
August 16th, 2016, 1:56 p.m.
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[Submitted] arm, config: Add an example ARM big.LITTLE(tm) configuration script
|
cdunham
|
July 8th, 2016, 10:28 a.m.
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[Submitted] x86: Implementation of Int3 and Int_Ib in long mode
|
chrism
|
June 28th, 2013, 1:25 p.m.
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[Submitted] x86: bugfix: lret instruction has to increment the stack pointer
|
chrism
|
April 17th, 2013, 4:37 a.m.
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[Discarded] util/m5: use CURDIR instead of PWD
|
cirosantilli
|
February 21st, 2018, 4:56 p.m.
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[Submitted] misc: Implement the Base SystemC Module as an sc_channel.
|
cmenard
|
January 9th, 2017, 12:17 p.m.
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[Submitted] misc: Fix order of object construction in the CxxConfigManager
|
cmenard
|
January 9th, 2017, 12:48 p.m.
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[Submitted] misc: fix includes in util/systemc
|
cmenard
|
February 5th, 2017, 2:05 p.m.
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[Submitted] misc: fix a compile error due to incompability with SystemC 2.3.1
|
cmenard
|
May 19th, 2016, 9:49 a.m.
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]
|
cmenard
|
January 30th, 2017, 4:40 p.m.
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]
|
cmenard
|
January 30th, 2017, 4:18 p.m.
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]
|
cmenard
|
January 30th, 2017, 4:13 p.m.
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]
|
cmenard
|
January 9th, 2017, 12:32 p.m.
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
|
cmenard
|
January 9th, 2017, 12:30 p.m.
|
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/10]
|
cmenard
|
November 7th, 2016, 4:43 p.m.
|
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]
|
cmenard
|
October 26th, 2016, 4:26 p.m.
|
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]
|
cmenard
|
June 23rd, 2016, 3:32 p.m.
|
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]
|
cmenard
|
January 31st, 2017, 10:57 a.m.
|
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[Submitted] misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]
|
cmenard
|
June 23rd, 2016, 3:32 p.m.
|
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[Submitted] misc: add a MasterId to the ExternalPort
|
cmenard
|
May 26th, 2016, 11:38 a.m.
|
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|
util: checkpoint_aggregator.py didn't work
|
cocoppang
|
September 20th, 2016, 7:13 a.m.
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