Review Board 2.0.15


  • Nilay Vaish

    nilay

    Nilay Vaish
    Last logged in June 6, 2016
    Joined June 1, 2010

nilay's review requests

Summary
Submitter Posted Last Updated
Moving Ruby to M5's debug print support
nilay
October 17th, 2010, 2:22 p.m.
NDEBUG for Ruby Assert statement
nilay
December 2nd, 2010, 1:23 p.m.
Hammer protocol: Change how data to copied from L1 to L2 cache and vice-versa
nilay
December 2nd, 2010, 11:01 a.m.
Add seed option to ruby_random_test.py
nilay
December 22nd, 2010, 8:45 p.m.
Replace WARN and ERROR statements in Ruby
nilay
December 2nd, 2010, 1:14 p.m.
Ruby: Fixes MESI CMP directory protocol
nilay
January 10th, 2011, 11:47 a.m.
Ruby: Updates MOESI CMP directory protocol
nilay
December 22nd, 2010, 2:22 p.m.
Ruby: Updates MOESI CMP token protocol
nilay
December 1st, 2010, 1:57 p.m.
Ruby: Updates MI cache coherence protocol
nilay
December 2nd, 2010, 11:01 a.m.
Ruby: Update MESI CMP Directory protocol
nilay
January 16th, 2011, 4:27 p.m.
Ruby: Updates MOESI Hammer protocol
nilay
October 27th, 2010, 12:35 p.m.
Change interface between coherence protocols and CacheMemory
nilay
December 21st, 2010, 9:18 a.m.
Ruby: Change PerfectSwitch's wakeup function
nilay
December 1st, 2010, 2 p.m.
Reorder Cache Lookup in Protocol Files
nilay
January 25th, 2011, 9:18 a.m.
Ruby: clean MOESI CMP directory protocol
nilay
February 18th, 2011, 5:59 a.m.
Ruby: Remove libruby_internal.hh
nilay
February 25th, 2011, 8:30 a.m.
Ruby: Remove store buffer
nilay
February 25th, 2011, 8:33 a.m.
Ruby: Remove libruby
nilay
January 25th, 2011, 9:21 a.m.
Ruby: Make DataBlock.hh independent of RubySystem
nilay
February 25th, 2011, 8:24 a.m.
Ruby: Make Address.hh independent of RubySystem
nilay
February 25th, 2011, 8:24 a.m.
Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
nilay
February 25th, 2011, 8:29 a.m.
SLICC: Remove the keyword wake_up_dependents
nilay
March 12th, 2011, 3:25 p.m.
SLICC: Remove the keyword wake_up_all_dependents
nilay
March 12th, 2011, 2:08 p.m.
SLICC: Remove external_type for structures
nilay
March 4th, 2011, 8:40 a.m.
Ruby: Convert AccessModeType to RubyAccessMode
nilay
March 18th, 2011, 9:53 p.m.
Ruby: Convert CacheRequestType to RubyRequestType
nilay
March 18th, 2011, 9:54 p.m.
Ruby: Remove CacheMsg class from SLICC
nilay
December 1st, 2010, 1:59 p.m.
Ruby: Correctly set access permissions for directory entries
nilay
May 6th, 2011, 3:50 p.m.
Ruby: Add support for functional accesses
nilay
March 29th, 2011, 2:53 p.m.
x86: Implements copyRegs() function
nilay
June 27th, 2011, 4:56 p.m.
SLICC: Put functions of a controller in its .cc file
nilay
July 26th, 2011, 9:02 a.m.
Scons: Drop RUBY as compile time option.
nilay
July 21st, 2011, 10:49 p.m.
Ruby: Remove files and includes not in use
nilay
July 26th, 2011, 8:59 a.m.
Ruby: Remove some unused code
nilay
August 24th, 2011, 9:42 p.m.
Ruby: Eliminate #define used for mapping of components
nilay
July 26th, 2011, 9:05 a.m.
[Discarded] IDE Disk: Bring it inline with QEMU
nilay
October 10th, 2011, 5:54 p.m.
MESI Coherence Protocol: Add calls for profiling misses
nilay
November 1st, 2011, 10:29 p.m.
[Discarded] X86 ISA: Change definitions of locked instructions
nilay
October 30th, 2011, 6:20 p.m.
x86: Add microop for fence
nilay
November 1st, 2011, 12:56 p.m.
Ruby: Change RubyPort and Sequencer to improve simulation speed
nilay
August 24th, 2011, 9:43 p.m.
SLICC: Use pointers for directory entries
nilay
December 5th, 2011, 1:58 a.m.
[Discarded] Simulation.py: Bug in setting switch_cpus
nilay
December 25th, 2011, 8:52 a.m.
X86 TLB: Move a DPRINTF to its correct place
nilay
December 31st, 2011, 10:34 a.m.
MESI Coherence Protocol: Fix L2 miss statistics
nilay
December 30th, 2011, 3:48 p.m.
eventq: add a function for replacing head of the queue
nilay
January 3rd, 2012, 4:04 p.m.
Config: Add an option of type 'choice' for cpu type
nilay
January 4th, 2012, 1:07 p.m.
Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh
nilay
January 3rd, 2012, 4:11 p.m.
AbstractController: Remove some of the unused functions
nilay
January 3rd, 2012, 4:14 p.m.
Ruby Cache: Add param for marking caches as instruction only
nilay
January 3rd, 2012, 4:17 p.m.
X86: Add memory fence to I/O instructions
nilay
December 30th, 2011, 3:37 p.m.
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