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[Discarded] mem: Align rules for sinking packets at the slave
|
ahansson
|
October 26th, 2015, 6:14 p.m.
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[Submitted] Packet: Remove NACKs from packet and its use in endpoints
|
ahansson
|
July 21st, 2012, 5:11 a.m.
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[Submitted] configs: Make the default memtest behaviour more complex
|
ahansson
|
December 9th, 2015, 11:51 p.m.
|
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[Submitted] AddrRange: Transition from Range<T> to AddrRange
|
ahansson
|
September 3rd, 2012, 9:22 p.m.
|
|
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[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
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|
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[Submitted] mem: Skip address mapper range checks to allow more flexibility
|
ahansson
|
December 6th, 2012, 8:02 p.m.
|
|
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[Submitted] mem: Add support for multi-channel DRAM configurations
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
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[Submitted] cpu: Remove CpuPort and use MasterPort in the CPU classes
|
ahansson
|
March 14th, 2013, 7 a.m.
|
|
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[Submitted] sim: Make MaxTick in Python match the one in C++
|
ahansson
|
July 12th, 2013, 9:41 a.m.
|
|
|
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[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (2/2)
|
ahansson
|
August 19th, 2013, 9:41 a.m.
|
|
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[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
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[Submitted] cpu: Useful getters for ActivityRecorder
|
ahansson
|
April 23rd, 2014, 12:26 p.m.
|
|
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[Submitted] power: Add basic DVFS support for gem5
|
ahansson
|
June 11th, 2014, 5:03 p.m.
|
|
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[Submitted] config: Update Streamline scripts and configs
|
ahansson
|
August 20th, 2014, 8:35 a.m.
|
|
|
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[Submitted] energy: Small extentions and fixes for DVFS handler
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] mem: Add DRAMPower wrapping class
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
|
|
|
[Submitted] mem: Assume all dynamic packet data is array allocated
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
|
[Submitted] dev: Add support for i2c devices
|
ahansson
|
March 18th, 2015, 4:41 p.m.
|
|
|
|
[Submitted] arm: Implement some missing syscalls (SE mode)
|
ahansson
|
May 8th, 2015, 1:11 p.m.
|
|
|
|
[Submitted] mem: Split WriteInvalidateReq into write and invalidate
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] mem: Tidy up packet
|
ahansson
|
July 13th, 2015, 3:15 p.m.
|
|
|
|
[Submitted] Python: Make the All proxy traverse SimObject children as well
|
ahansson
|
March 21st, 2012, 10:07 a.m.
|
|
|
|
[Submitted] Bus: Remove redundant packet parameter from isOccupied
|
ahansson
|
May 25th, 2012, 9:47 a.m.
|
|
|
|
[Submitted] ext: Replace gzstream with iostream3 from zlib to avoid LGPL
|
ahansson
|
December 28th, 2015, 6:15 p.m.
|
|
|
|
[Submitted] Checker: Fix checker CPU ports
|
ahansson
|
August 25th, 2012, 4 a.m.
|
|
|
|
[Submitted] Ruby: Bump the stats after recent memory controller changes
|
ahansson
|
September 10th, 2012, 8:49 a.m.
|
|
|
|
[Submitted] scons: Enable building with the gcc/clang Address Sanitizer
|
ahansson
|
February 15th, 2016, 9 a.m.
|
|
|
|
[Submitted] config: Use shared cache config for regressions
|
ahansson
|
October 24th, 2012, 7:13 a.m.
|
|
|
|
[Submitted] config: Add a check for fastmem only used with Atomic CPU
|
ahansson
|
October 25th, 2012, 10:35 a.m.
|
|
|
|
[Submitted] sim: Make clock private and access using clockPeriod()
|
ahansson
|
February 14th, 2013, 1:52 a.m.
|
|
|
|
[Submitted] tests: Prune 00.gzip from the regressions
|
ahansson
|
June 6th, 2013, 2:28 p.m.
|
|
|
|
[Submitted] mem: Rename SimpleDRAM to a more suitable DRAMCtrl
|
ahansson
|
March 7th, 2014, 11:47 p.m.
|
|
|
|
[Submitted] arm: quick hack to allow a greater number of CPUs to a guest OS
|
ahansson
|
April 23rd, 2014, 12:16 p.m.
|
|
|
|
[Submitted] mem: Simplify DRAM response scheduling
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] arm: use condition code registers for ARM ISA
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
|
|
|
[Submitted] x86: Flag instructions that call suspend as IsQuiesce
|
ahansson
|
August 28th, 2014, 7:31 a.m.
|
|
|
|
[Submitted] alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
|
ahansson
|
September 11th, 2014, 2:01 p.m.
|
|
|
|
[Submitted] sim: Add typedefs for PMU probe points
|
ahansson
|
September 29th, 2014, 10:38 a.m.
|
|
|
|
[Submitted] mem: Add parameter to reserve MSHR entries for demand access
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] arm: Remove the 'magic MSI register' in the GIC (PL390)
|
ahansson
|
March 6th, 2015, 1:39 p.m.
|
|
|
|
[Submitted] arch, cpu: Do not forward snoops to table walker
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] MEM: Add the system port as a central access point
|
ahansson
|
December 19th, 2011, 5:52 a.m.
|
|
|
|
[Submitted] Ruby: Simplify tester ports by not using SimpleTimingPort
|
ahansson
|
February 16th, 2012, 10:45 a.m.
|
|
|
|
[Submitted] util: Enable DRAM sweep to print power and efficiency
|
ahansson
|
July 16th, 2015, 3:43 p.m.
|
|
|
|
[Submitted] mem: Use C++11 delegating constructors for Request
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] config: Update memtest to stress test clean writebacks
|
ahansson
|
October 19th, 2015, 5:03 p.m.
|
|
|
|
[Submitted] mem: Remove unused cache stats
|
ahansson
|
February 24th, 2016, 9:29 a.m.
|
|
|
|
[Submitted] mem: Add tracing support in the communication monitor
|
ahansson
|
December 6th, 2012, 7:52 p.m.
|
|
|
|
stats: Add length of all stats to the SQL stats table
|
ahansson
|
January 15th, 2013, 10:33 a.m.
|
|
