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[Submitted] ARM: Update m5op assembly for thumb compilation.
|
ali
|
May 2nd, 2012, 1:07 p.m.
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[Submitted] Cache: Panic if you attempt to create a checkpoint with a cache in the system
|
ali
|
May 2nd, 2012, 1:07 p.m.
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[Submitted] gcc: Enable Link-Time Optimization for gcc >= 4.6
|
ahansson
|
May 2nd, 2012, 11:24 a.m.
|
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[Submitted] Packet: Cleaning up packet command and attribute
|
ahansson
|
May 2nd, 2012, 7:14 a.m.
|
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[Submitted] Syscalls: panic when the length argument to mmap is excessive.
|
gblack
|
April 29th, 2012, 2:38 a.m.
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[Submitted] X86: Split Condition Code register
|
nilay
|
April 27th, 2012, 8 a.m.
|
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[Submitted] scons: allow override of SWIG binary on command line
|
stever
|
April 23rd, 2012, 9:25 a.m.
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[Submitted] ISA: Put parser generated files in a "generated" directory.
|
gblack
|
April 22nd, 2012, 11:28 p.m.
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[Discarded] X86: Break flags in to read and write sets
|
nilay
|
April 21st, 2012, 1:28 p.m.
|
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[Discarded] X86: Runtime read, write conditions for CCFlagBits register
|
nilay
|
April 21st, 2012, 1:20 p.m.
|
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[Submitted] MEM: Add the communication monitor
|
ahansson
|
April 20th, 2012, 11:23 a.m.
|
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[Submitted] clang/gcc: Use STL hash function for int64_t and uint64_t
|
ahansson
|
April 18th, 2012, 9:52 p.m.
|
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[Submitted] X86: Report an error if there's no kernel object, don't blindly use it.
|
gblack
|
April 18th, 2012, 1:55 a.m.
|
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[Submitted] base: Include cassert in trie.hh.
|
gblack
|
April 17th, 2012, 5:20 a.m.
|
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[Submitted] X86: Clear out duplicate TLB entries when adding a new one.
|
gblack
|
April 17th, 2012, 5:20 a.m.
|
|
|
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[Discarded] ISA Parser: runtime read, write conditions for registers
|
nilay
|
April 16th, 2012, 9:52 p.m.
|
|
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[Submitted] ISA Parser: Allow predication of source and destination registers
|
nilay
|
April 16th, 2012, 9:52 p.m.
|
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[Discarded] X86: Add ext and cc fields to FP microops
|
nilay
|
April 16th, 2012, 9:52 p.m.
|
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|
|
[Submitted] SE Config: Changed se.py to support multithreaded mode
|
jayneel
|
April 16th, 2012, 11:53 a.m.
|
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|
|
[Submitted] Config: Add command line options for disk image and memory size
|
jayneel
|
April 16th, 2012, 11:38 a.m.
|
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|
|
[Submitted] CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
|
gblack
|
April 15th, 2012, 1:17 a.m.
|
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|
[Discarded] x86: Different microop if all flag bits are written
|
nilay
|
April 12th, 2012, 5:37 p.m.
|
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|
[Submitted] MEM: Separate requests and responses for timing accesses
|
ahansson
|
April 11th, 2012, 8:23 a.m.
|
|
|
|
[Submitted] Ruby: Ensure order-dependent iteration uses an ordered map
|
ahansson
|
April 10th, 2012, 10:18 a.m.
|
|
|
|
[Submitted] MEM: Use base class Master/SlavePort pointers in the bus
|
ahansson
|
April 9th, 2012, 9:40 a.m.
|
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|
[Submitted] X86: Use the AddrTrie class to implement the TLB.
|
gblack
|
April 8th, 2012, 12:59 a.m.
|
|
|
|
[Discarded] tests: Add a unit test for the new AddrTrie data structure.
|
gblack
|
April 8th, 2012, 12:57 a.m.
|
|
|
|
[Submitted] sim: A trie data structure specifically to speed up paging lookups.
|
gblack
|
April 8th, 2012, 12:57 a.m.
|
|
|
|
[Submitted] tests: Fix building unit tests.
|
gblack
|
April 8th, 2012, 12:56 a.m.
|
|
|
|
[Submitted] MEM: Add the PortId type and a corresponding id field to Port
|
ahansson
|
April 7th, 2012, 9:51 a.m.
|
|
|
|
[Submitted] Regression: Add ANSI colours to highlight test status
|
ahansson
|
April 6th, 2012, 9:16 a.m.
|
|
|
|
[Submitted] NetworkTest: remove unnecessary memory allocation
|
tushar
|
April 5th, 2012, 2:20 p.m.
|
|
|
|
[Submitted] ruby: set SimpleTiming as the default cpu
|
beckmann
|
April 4th, 2012, 10:02 p.m.
|
|
|
|
[Submitted] slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
|
beckmann
|
April 4th, 2012, 10:01 p.m.
|
|
|
|
[Submitted] sim-ruby: checkpointing fixes and dependent eventq improvements
|
beckmann
|
April 4th, 2012, 10:01 p.m.
|
|
|
|
[Submitted] MOESI_hammer: tbe allocation and dependent wakeup fixes
|
beckmann
|
April 4th, 2012, 10 p.m.
|
|
|
|
[Submitted] python: added __nonzero__ function to SimObject Bool params
|
beckmann
|
April 4th, 2012, 9:59 p.m.
|
|
|
|
[Discarded] request: added split Paddr function
|
beckmann
|
April 4th, 2012, 9:58 p.m.
|
|
|
|
[Submitted] MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality
|
beckmann
|
April 4th, 2012, 9:58 p.m.
|
|
|
|
[Submitted] rubytest: seperated read and write ports.
|
beckmann
|
April 4th, 2012, 9:56 p.m.
|
|
|
|
[Submitted] Ruby: Fix the example configurations option parsing
|
ahansson
|
April 4th, 2012, 3:44 p.m.
|
|
|
|
[Submitted] Ruby: Use MasterPort base-class pointers where possible
|
ahansson
|
April 4th, 2012, 10:22 a.m.
|
|
|
|
[Discarded] o3: move arm_v7a-like config to the o3 directory
|
ksewell
|
April 4th, 2012, 7:19 a.m.
|
|
|
|
[Submitted] MEM: Remove the Broadcast destination from the packet
|
ahansson
|
April 4th, 2012, 12:52 a.m.
|
|
|
|
[Discarded] Config: Partially roll back changeset 8920
|
nilay
|
April 3rd, 2012, 9:43 p.m.
|
|
|
|
[Submitted] clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
|
ahansson
|
April 2nd, 2012, 12:41 p.m.
|
|
|
|
[Submitted] MEM: Separate snoops and normal memory requests/responses
|
ahansson
|
April 2nd, 2012, 6:49 a.m.
|
|
|
|
[Submitted] ARM: fix value of MISCREG_CTR returned by readMiscReg()
|
atgutier
|
March 31st, 2012, 8:35 a.m.
|
|
|
|
[Submitted] CPU: Unify initMemProxies across CPUs and simulation modes
|
ahansson
|
March 27th, 2012, 3:55 a.m.
|
|
|
|
[Submitted] Config: Change the way options are added
|
nilay
|
March 24th, 2012, 1:30 p.m.
|
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