Review Board 2.0.15


All Review Requests

Summary
Submitter Posted Last Updated
cpu: Fix Checker register index use
ahansson
November 5th, 2013, 4:34 p.m.
cpu: fix case with o3 cpu blocking and unblocking decode in cycle
ali
January 22nd, 2013, 1:47 p.m.
cpu: Fix cache blocked load behavior in o3 cpu
ahansson
August 13th, 2014, 2:06 p.m.
cpu: fix bug when TrafficGen deschedules event
rioshering
August 19th, 2013, 7:52 a.m.
CPU: Fix bug when a split transaction is issued to a faster cache
ali
November 11th, 2010, 4:12 p.m.
cpu: Fix BTB threading oversight
cdunham
February 23rd, 2016, 8:58 p.m.
cpu: Fix broken thread context handover
ali
December 6th, 2012, 12:13 p.m.
cpu: Fix broken squashAfter implementation in O3 CPU
ali
December 6th, 2012, 12:05 p.m.
cpu: fix a switching issue with the o3 cpu.
ali
February 25th, 2013, 9:54 a.m.
cpu: Fix a livelock in the o3 cpu.
ali
January 22nd, 2013, 1:45 p.m.
CPU: Fix a case where timing simple cpu faults can nest.
ali
May 2nd, 2011, 3:20 p.m.
cpu: Fix a bug in the O3 CPU introduced by the cache line patch
ahansson
August 7th, 2013, 3:12 p.m.
cpu: Fix a bug in counting issued instructions in MinorCPU
ahansson
May 8th, 2015, 1:11 p.m.
cpu: Ensure timing CPU sinks response before sending new request
ahansson
January 27th, 2015, 10:19 a.m.
cpu: Enforce 1 interrupt controller per thread
cdunham
October 5th, 2015, 6:52 p.m.
cpu: Encapsulate traffic generator input in a stream
ahansson
December 6th, 2012, 7:54 p.m.
cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU
ctorng
January 30th, 2014, 9:29 p.m.
cpu: Dynamically instantiate O3 CPU LSQUnits
jthestness
July 19th, 2013, 5:35 p.m.
cpu: DRAM Traffic Generator
ahansson
March 7th, 2014, 11:37 p.m.
cpu: discard nops at decode in o3
mhayenga
March 29th, 2013, 7:27 p.m.
cpu: disallow speculative update of the conditional branch predictor tables (o3)
aperais
November 18th, 2016, 3:14 p.m.
cpu: Create record type enum for elastic traces
cdunham
September 3rd, 2015, 4:17 p.m.
cpu: Correctly call parent on switchOut() and takeOverFrom()
ali
December 6th, 2012, 11:59 a.m.
cpu: Construct ROB with cpu params struct instead of each variable
ali
October 17th, 2013, 4:58 p.m.
cpu: Consider instructions waiting for FU completion in draining
ahansson
June 4th, 2013, 10:01 a.m.
cpu: commit probe notification on every microop or macroop
nnikoleris
January 14th, 2015, 10:42 a.m.
cpu: clean up architectural register classification
stever
August 22nd, 2013, 12:37 a.m.
CPU: Check that the interrupt controller is created when needed
ahansson
March 2nd, 2012, 4:45 a.m.
cpu: Change writeback modeling for outstanding instructions
ali
June 12th, 2014, 10:48 p.m.
cpu: Change traffic generators to use different values for writes
nnikoleris
November 18th, 2016, 2:53 p.m.
cpu: Change thread assignents for heterogenous SMT
cdunham
July 30th, 2015, 6:46 p.m.
cpu: change comments in tournament branch predictor to reflect what the code does
aperais
November 18th, 2016, 12:41 p.m.
cpu: Block traffic generator when requests have to retry
ahansson
April 23rd, 2013, 12:29 a.m.
cpu: Always mask the snoop address when performing lock check
ahansson
November 24th, 2014, 12:20 p.m.
cpu: allow the fetch buffer to be smaller than a cache line
atgutier
February 18th, 2013, 8:20 a.m.
cpu: Allow setWhen on trace objects
ahansson
April 23rd, 2014, 12:24 p.m.
cpu: Adjust for trace offset and fix stats
andysan
August 12th, 2016, 4:45 p.m.
cpu: Adding AddressMonitor structs for every hardware thread
alexdutu
May 28th, 2015, 3:40 p.m.
cpu: Added interface for vector reg file
Rekai
December 9th, 2016, 6:44 p.m.
cpu: added assertions to ensure the correct proxies are used
beckmann
July 2nd, 2012, 10 p.m.
cpu: Add TraceCPU to playback elastic traces
cdunham
August 11th, 2015, 9:05 p.m.
cpu: Add support for scheduling multiple inst/load stop events
andysan
June 3rd, 2013, 5:26 a.m.
cpu: Add support for protobuf input for the trace generator
ahansson
December 6th, 2012, 7:58 p.m.
cpu: add support for outputing a protobuf formatted CPU trace
ali
December 10th, 2014, 5:57 p.m.
cpu: Add support for Memory+Barrier instruction types in O3 cpu.
ali
November 30th, 2013, 11:39 p.m.
cpu: Add support for instructions that zero cache lines.
ali
November 30th, 2013, 11:51 p.m.
[Discarded] cpu: Add store-access operations
atgutier
October 30th, 2015, 9:50 p.m.
cpu: Add store-access operations
atgutier
May 11th, 2015, 10:22 p.m.
CPU: Add some useful debug message to the timing simple cpu.
ali
May 2nd, 2011, 3:21 p.m.
cpu: Add SMT support to MinorCPU
cdunham
February 23rd, 2016, 8:58 p.m.
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