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[Submitted] arm: Make sure UndefinedInstructions are properly initialized
|
ahansson
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April 23rd, 2014, 12:27 p.m.
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[Submitted] mem: Make DRAM read/write switching less conservative
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
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[Submitted] mem: Ensure DRAM refresh respects timings
|
ahansson
|
April 23rd, 2014, 12:33 p.m.
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[Submitted] mem: Add DRAM power states to the controller
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
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[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
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[Submitted] mem: Add tWR to DRAM activate and precharge constraints
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
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[Submitted] mem: Merge DRAM latency calculation and bank state update
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
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[Submitted] mem: Add tRTP to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
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[Submitted] mem: Remove printing of DRAM params
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
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[Submitted] mem: Add precharge all (PREA) to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
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[Submitted] mem: Simplify DRAM response scheduling
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
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[Submitted] mem: Add DRAM cycle time
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
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[Submitted] mem: Update DDR3 and DDR4 based on datasheets
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
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[Submitted] tests: Reflect name change in DRAM tests
|
ahansson
|
April 23rd, 2014, 12:38 p.m.
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[Submitted] syscall emulation: clean up & comment SyscallReturn
|
stever
|
April 21st, 2014, 7:15 p.m.
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cache: enable multiple stores per cycle
|
stever
|
May 14th, 2014, 5:46 a.m.
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o3: issue excl. prefetch as soon as store address is available
|
stever
|
May 14th, 2014, 5:47 a.m.
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[Submitted] config: remove unecessary assignment of etherlink interfaces
|
atgutier
|
May 15th, 2014, 4:03 p.m.
|
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[Submitted] ruby: message buffer: drop dequeue_getDelayCycles()
|
nilay
|
March 13th, 2014, 5:35 a.m.
|
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[Submitted] Config: A patch from Nilay which fixes running SMT workloads with se.py.
|
gblack
|
May 25th, 2012, 12:51 a.m.
|
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[Submitted] Ruby: Make it so that controllers attached to Sequencers don't have to be named L1Cache.
|
hsul
|
October 11th, 2011, 1:22 p.m.
|
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[Submitted] style: eliminate equality tests with true and false
|
stever
|
June 1st, 2014, 12:47 a.m.
|
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[Submitted] Util: Do not style check symlinks
|
jthestness
|
June 7th, 2014, 10 p.m.
|
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[Submitted] sim: More rigorous clocking comments
|
jthestness
|
June 7th, 2014, 10:02 p.m.
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[Submitted] scons: Bump the compiler version to gcc 4.6 and clang 3.0
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
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[Submitted] ext: McPAT interface changes and fixes
|
yxw0985
|
December 11th, 2013, 10:48 p.m.
|
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[Submitted] ext: Add a McPAT regression tester
|
yxw0985
|
December 11th, 2013, 10:48 p.m.
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[Submitted] ext: Redirect McPAT object files
|
yxw0985
|
January 22nd, 2014, 1:33 a.m.
|
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[Submitted] x86: fix table walker assertion
|
stever
|
May 14th, 2014, 5:46 a.m.
|
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[Submitted] o3: make LSQ full check more selective
|
stever
|
May 14th, 2014, 5:46 a.m.
|
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[Submitted] o3: split load & store queue full cases
|
stever
|
May 14th, 2014, 5:46 a.m.
|
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[Submitted] arm: make the bi-mode predictor the default for O3_ARM_v7a_BP
|
atgutier
|
February 21st, 2014, 10:14 p.m.
|
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[Submitted] cpu: implement bi-mode-style branch predictor
|
atgutier
|
February 21st, 2014, 10:19 p.m.
|
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[Submitted] mem: DRAMPower trace formatting script
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
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[Submitted] power: Add basic DVFS support for gem5
|
ahansson
|
June 11th, 2014, 5:03 p.m.
|
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[Submitted] mem: DRAMPower trace output
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
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[Submitted] mem: Add bank and rank indices as fields to the DRAM bank
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
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[Submitted] arm: Add support for ARMv8 (AArch64 & AArch32)
|
ali
|
January 8th, 2014, 8:11 p.m.
|
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[Submitted] base: fix some bugs in EthAddr
|
atgutier
|
June 26th, 2014, 9:49 p.m.
|
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[Submitted] kern: get rid of unused linux syscall files
|
stever
|
July 3rd, 2014, 5:13 p.m.
|
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[Submitted] syscall emulation: fix DPRINTF arg ordering bug
|
stever
|
July 3rd, 2014, 5:12 p.m.
|
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|
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[Submitted] sim: remove unused MemoryModeStrings array
|
stever
|
June 24th, 2014, 6:12 a.m.
|
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[Submitted] x86: make PioBus return BadAddress errors
|
stever
|
June 21st, 2014, 4:53 p.m.
|
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[Submitted] mem: refactor LRU cache tags and add random replacment tags
|
atgutier
|
February 21st, 2014, 10:11 p.m.
|
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[Submitted] arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
|
atgutier
|
February 21st, 2014, 10:18 p.m.
|
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|
|
[Submitted] cpu: `Minor' in-order CPU model
|
ali
|
May 30th, 2014, 3:23 p.m.
|
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|
|
[Discarded] Different SimpleDRAM latency for read and write access
|
senni
|
December 5th, 2013, 10:23 a.m.
|
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[Submitted] config: Add hooks to enable new config sys
|
ahansson
|
April 23rd, 2014, 12:22 p.m.
|
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[Submitted] config: Add SubSystem container for simobjects
|
ahansson
|
July 28th, 2014, 5:50 a.m.
|
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[Submitted] scons: Warn for incompatible gcc and binutils
|
ahansson
|
July 28th, 2014, 5:50 a.m.
|
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