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[Submitted] O3: Send instruction back to fetch on squash to seed predecoder correctly.
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ali
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February 25th, 2011, 8:58 p.m.
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[Submitted] ARM: Identify branches as conditional or unconditional and direct or indirect.
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ali
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March 11th, 2011, 3:19 p.m.
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[Submitted] mem: fix cache stats to use request ids correctly
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ali
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February 4th, 2012, 12:24 p.m.
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[Submitted] base: Check for static_assert support and provide fallback
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ali
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September 7th, 2012, 12:23 p.m.
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[Submitted] python: Rename doDrain()->drain() and make it do the right thing
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ali
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October 24th, 2012, 2:52 p.m.
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[Submitted] cpu: rename the misleading inSyscall to noSquashFromTC
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ali
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December 6th, 2012, 11:45 a.m.
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[Submitted] arm: Enable support for triggering a sim panic on kernel panics
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ali
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February 13th, 2013, 8:48 a.m.
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[Submitted] cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
|
ali
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November 30th, 2013, 11:49 p.m.
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[Submitted] ARM: Add system for ARM/Linux and bootstrapping
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ali
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August 13th, 2010, 9:40 a.m.
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[Discarded] ARM: make predicated-false instruction to move data from a old register.
|
ali
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August 13th, 2010, 10:03 a.m.
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[Submitted] ARM: Seperate the queues of L1 and L2 walker states.
|
ali
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August 23rd, 2010, 9:32 a.m.
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[Submitted] ARM: Fix SRS instruction to micro-code memory operation and register update.
|
ali
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November 11th, 2010, 4:12 p.m.
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[Submitted] o3: Fix front-end pipeline interlock behavior
|
ali
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June 12th, 2014, 10:49 p.m.
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[Submitted] O3: Fix itstate prediction and recovery.
|
ali
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January 12th, 2011, 9:09 a.m.
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[Submitted] ARM: Implement L2CTLR num cpus register.
|
ali
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July 13th, 2011, 8:57 a.m.
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[Submitted] gem5ops: Implement Java JNI for gem5Ops
|
ali
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August 19th, 2011, 3:19 p.m.
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[Submitted] O3: Add stat that counts how many cycles the O3 cpu was quiesced.
|
ali
|
November 3rd, 2011, 1:23 p.m.
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[Submitted] ARM: Add support for running multiple systems
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ali
|
December 16th, 2011, 1:31 p.m.
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[Submitted] stats: Provide a mechanism to get a callback when stats are dumped.
|
ali
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February 13th, 2012, 3:41 p.m.
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[Submitted] cpu: Make sure that a drained timing CPU isn't executing ucode
|
ali
|
December 6th, 2012, 12:16 p.m.
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[Submitted] O3: Handle loads when the destination is the PC.
|
ali
|
August 13th, 2010, 9:51 a.m.
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[Submitted] ARM: Implement functional virtual to physical address translation
|
ali
|
September 16th, 2010, 12:47 a.m.
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[Submitted] O3: Support squashing all state after special instruction
|
ali
|
November 19th, 2010, 4:06 p.m.
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[Submitted] ARM: Construct the predicate test register for more instruction programatically.
|
ali
|
May 4th, 2011, 6:44 p.m.
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[Submitted] ARM: Add support for Versatile Express extended memory map
|
ali
|
February 22nd, 2012, 12:03 p.m.
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[Submitted] Cache: Panic if you attempt to create a checkpoint with a cache in the system
|
ali
|
May 2nd, 2012, 1:07 p.m.
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[Submitted] sim: Include object header files in SWIG interfaces
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] ARM: Finish the timing translation when taking a fault.
|
ali
|
August 13th, 2010, 9:39 a.m.
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[Submitted] ARM: Don't write tracedata in completeAcc as we might hav freed it already
|
ali
|
August 13th, 2010, 9:58 a.m.
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[Submitted] ARM: Use less micro-ops for register update loads if possible.
|
ali
|
August 23rd, 2010, 9:30 a.m.
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[Submitted] Mem: Finish half-baked support for mmaping file in physmem.
|
ali
|
October 2nd, 2010, 7:12 p.m.
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[Submitted] O3: Make all instructions that write a misc register not perform the write until commit.
|
ali
|
November 8th, 2010, 3:39 p.m.
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[Submitted] O3: Don't try to scoreboard misc registers.
|
ali
|
December 6th, 2010, 3:58 p.m.
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[Submitted] ARM: Do something for ISB, DSB, DMB
|
ali
|
February 11th, 2011, 4:40 p.m.
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[Submitted] ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
|
ali
|
March 30th, 2011, 2:52 p.m.
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[Submitted] cpu: add support for outputing a protobuf formatted CPU trace
|
ali
|
December 10th, 2014, 5:57 p.m.
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[Submitted] O3: Fix offset calculation into storeQueue buffer for store->load forwarding
|
ali
|
May 16th, 2011, 2:35 p.m.
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[Submitted] LSQ: Only trigger a memory violation with a load/load if the value changes.
|
ali
|
August 9th, 2011, 12:35 p.m.
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[Submitted] scons: Make compiler version error more verbose and easier to debug.
|
ali
|
June 7th, 2012, 10:46 a.m.
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[Submitted] cpu: Unify SimpleCPU and O3 CPU serialization code
|
ali
|
December 6th, 2012, 11:58 a.m.
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[Submitted] cpu: Construct ROB with cpu params struct instead of each variable
|
ali
|
October 17th, 2013, 4:58 p.m.
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[Submitted] ARM: Add some registers for big loads/stores to support neon.
|
ali
|
August 13th, 2010, 9:49 a.m.
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[Submitted] SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.
|
ali
|
January 18th, 2011, 2:33 p.m.
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[Submitted] CheckerCPU: Re-factor CheckerCPU to be compatible current state of gem5
|
ali
|
November 3rd, 2011, 1:27 p.m.
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[Submitted] cache: Allow main memory to be at disjoint address ranges.
|
ali
|
March 6th, 2012, 4:54 p.m.
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[Submitted] sim: Provide a framework for detecting out of data checkpoints and migrating them.
|
ali
|
May 30th, 2012, 9:34 a.m.
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[Submitted] sim: add validation to make sure there is memory where we're loading the kernel
|
ali
|
August 16th, 2012, 1:26 p.m.
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[Submitted] base: Fix a few incorrectly handled print format cases
|
ali
|
October 24th, 2012, 2:20 p.m.
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[Submitted] sim, arch: Add support for invalidating TLBs when draining
|
ali
|
November 2nd, 2012, 10:11 a.m.
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[Submitted] config: Remove O3 dependencies
|
ali
|
January 7th, 2013, 11:25 a.m.
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