Review Board 2.0.15


Review requests for Default

Summary Submitter
Posted Last Updated
tests: Recategorise regressions based on run time
ahansson
March 6th, 2015, 1:40 p.m.
mem, alpha: Move Alpha-specific request flags
ahansson
March 30th, 2015, 9:17 a.m.
SPARC: Fixing a minor copy-paste bug using the wrong variable
ahansson
November 24th, 2011, 10:04 a.m.
MEM: Remove the notion of the default port
ahansson
December 19th, 2011, 5:56 a.m.
MEM: Simplify cache ports preparing for master/slave split
ahansson
February 21st, 2012, 3:21 a.m.
MEM: Introduce the master/slave port sub-classes in C++
ahansson
March 10th, 2012, 11:54 a.m.
mem: Add CleanEvict and Writeback support to snoop filters
ahansson
August 19th, 2015, 9:07 a.m.
Packet: Cleaning up packet command and attribute
ahansson
May 2nd, 2012, 7:14 a.m.
misc: Appease clang static analyzer
ahansson
October 26th, 2015, 6:13 p.m.
gcc: Fix warnings for gcc 4.7 and clang 3.1
ahansson
June 27th, 2012, 10:36 a.m.
AddrRange: Remove unused range_multimap
ahansson
September 3rd, 2012, 9:21 p.m.
Mem: Tidy up bus member variables types
ahansson
September 20th, 2012, 6:39 a.m.
cpu: Share the send functionality between traffic generators
ahansson
December 6th, 2012, 7:59 p.m.
mem: Merge ranges in bus before passing them on
ahansson
February 19th, 2013, 6:38 a.m.
[Discarded] sim: Pre-compute the clock period
ahansson
May 27th, 2013, 11:25 a.m.
cpu: Move the branch predictor out of the BaseCPU
ahansson
August 19th, 2013, 9:38 a.m.
mem: Make tXAW enforcement less conservative and per rank
ahansson
October 16th, 2013, 7:42 a.m.
cpu: Timebuf const accessors
ahansson
April 23rd, 2014, 12:25 p.m.
arch, cpu: Factor out the ExecContext into a proper base class
ahansson
August 19th, 2014, 9:28 a.m.
mem: Add memory rank-to-rank delay
ahansson
September 10th, 2014, 7:52 a.m.
mem: Remove DRAMSim2 DDR3 configuration
ahansson
September 29th, 2014, 10:41 a.m.
mem: Use const pointers for port proxy write functions
ahansson
November 17th, 2014, 6:14 a.m.
mem: Always use SenderState for response routing in RubyPort
ahansson
January 5th, 2015, 4:50 p.m.
style: Fix broken m5format command
ahansson
February 5th, 2015, 10:59 a.m.
mem: Cleanup flow for uncacheable accesses
ahansson
March 17th, 2015, 7:10 p.m.
misc: Appease gcc 5.1
ahansson
May 8th, 2015, 1:10 p.m.
mem: Allow read-only caches and check compliance
ahansson
June 10th, 2015, 7:59 a.m.
MEM: Remove legacy DRAM in preparation for memory updates
ahansson
March 21st, 2012, 10:04 a.m.
MEM: Separate requests and responses for timing accesses
ahansson
April 11th, 2012, 8:23 a.m.
mem: Deduce if cache should forward snoops
ahansson
December 28th, 2015, 6:14 p.m.
TrafficGen: Add a basic traffic generator regression
ahansson
August 24th, 2012, 11:20 a.m.
mem: Align downstream cache packet creation in atomic and timing
ahansson
March 31st, 2016, 6:21 p.m.
mem: Add predecessor to SenderState base class
ahansson
February 14th, 2013, 1:48 a.m.
mem: Spring cleaning of MSHR and MSHRQueue
ahansson
May 9th, 2013, 3:18 a.m.
config: Command line support for multi-channel memory
ahansson
July 19th, 2013, 8:35 a.m.
mem: Edit proto Packet and enhance the python script
ahansson
February 21st, 2014, 1:30 p.m.
mem: Add close adaptive paging policy to DRAM controller model
ahansson
March 7th, 2014, 11:44 p.m.
arch: remove inline specifiers on all inst constrs, all ISAs
ahansson
April 23rd, 2014, 12:14 p.m.
mem: Remove printing of DRAM params
ahansson
April 23rd, 2014, 12:36 p.m.
tests: Use O3_ARM_v7a config for full-system ARM regressions
ahansson
August 13th, 2014, 2:07 p.m.
cpu: Fix o3 drain bug
ahansson
August 27th, 2014, 4:15 p.m.
tests: Use more representative configs for ARM tests
ahansson
September 10th, 2014, 7:54 a.m.
cpu: Remove Ozone CPU from the source tree
ahansson
September 29th, 2014, 10:38 a.m.
misc: Use gmtime for conversion to UTC to avoid getenv/setenv
ahansson
October 14th, 2014, 7:55 a.m.
config: Expose the DRAM ranks as a command-line option
ahansson
December 12th, 2014, 5:46 p.m.
cpu: Tidy up the MemTest and make false sharing more obvious
ahansson
January 21st, 2015, 1:23 p.m.
mem: Split port retry for all different packet classes
ahansson
February 7th, 2015, 5:24 p.m.
mem: Add missing stats update for uncacheable MSHRs
ahansson
March 30th, 2015, 9:16 a.m.
mem: Avoid DRAM write queue iteration for merging and read lookup
ahansson
April 24th, 2015, 4:32 p.m.
MAC: Make gem5 compile and run on MacOSX 10.7.2
ahansson
December 19th, 2011, 5:50 a.m.
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