Review Board 2.0.15


Review requests for Default

Summary Submitter
Posted Last Updated
O3CPU: Idle CPU status logic revised
alexdutu
January 21st, 2015, midnight
cpu, o3: Checking AddressMonitor structures on every store for SMT
alexdutu
May 28th, 2015, 3:40 p.m.
cpu: o3: Mapping the ZeroRegister for all hardware threads
alexdutu
May 28th, 2015, 3:38 p.m.
mem: Page Table long lines
alexdutu
September 30th, 2014, 7:32 p.m.
cpu, o3: Remove assertion on buffer from rename being empty
alexdutu
May 28th, 2015, 3:41 p.m.
Mem: adding a multi-level page table class
alexdutu
July 11th, 2014, 3:57 p.m.
x86, o3: Enabling x86 TLBs for multiple hardware threads
alexdutu
May 28th, 2015, 3:38 p.m.
Mem: adding architectural page table support for SE mode
alexdutu
July 28th, 2014, 10:30 p.m.
mem: Page Table map api modification
alexdutu
October 6th, 2014, 6:58 p.m.
x86: Mwait reimplementation
alexdutu
May 28th, 2015, 3:41 p.m.
gpu-compute: Added method to compute the actual workgroup size
alexdutu
September 27th, 2016, 8:50 p.m.
kvm, x86: Adding support for SE mode execution
alexdutu
July 11th, 2014, 4:01 p.m.
[Discarded] x86, o3: Enabling x86 TLBs for multiple hardware threads
alexdutu
May 28th, 2015, 3:38 p.m.
cpuid, x86: Enabling more features in CPUid
alexdutu
August 1st, 2014, 3:48 p.m.
cpu: o3: Merging haltContext with suspendContext
alexdutu
May 26th, 2015, 4:45 p.m.
misc: Adds a warning in case gdb is attached multiple times
alexdutu
September 27th, 2016, 10:08 p.m.
cpu: o3: Fetch stage updates for hw threads priority list
alexdutu
May 28th, 2015, 3:39 p.m.
SegInit, x86: Segment initialization to support KvmCPU in SE
alexdutu
August 1st, 2014, 3:53 p.m.
kvm: Adding details to kvm page fault in x86
alexdutu
September 27th, 2016, 10:10 p.m.
cpu: o3: Commit stage updates for hw threads priority list
alexdutu
May 28th, 2015, 3:40 p.m.
ARM: Use a stl queue for the table walker state
ali
August 13th, 2010, 9:39 a.m.
ARM: Implement CLREX init/complete acc methods
ali
August 13th, 2010, 9:58 a.m.
ARM: Set the high bits in the part number so it's considered new by some code.
ali
August 23rd, 2010, 9:30 a.m.
Bus: Have the I/O devices that return address ranges print them out.
ali
October 2nd, 2010, 7:12 p.m.
imported patch ext/simd_opclasses.patch
ali
November 8th, 2010, 3:32 p.m.
The ARM decoder should not panic when decoding undefined holes in the
ali
December 6th, 2010, 3:57 p.m.
M5: Don't include isa_traits.hh and use the TheISA namespace unless really needed.
ali
February 11th, 2011, 4:39 p.m.
ARM: Fix bug in MicroLdrNeon templates for initiateAcc().
ali
March 30th, 2011, 2:51 p.m.
arm: always set the IsFirstMicroop flag
ali
December 10th, 2014, 5:56 p.m.
O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
ali
May 16th, 2011, 2:35 p.m.
Mem: Put prefetcher notify call before packet is deleted.
ali
August 9th, 2011, 12:34 p.m.
cpu: Initialize the O3 pipeline from startup()
ali
December 6th, 2012, 11:56 a.m.
util: Add a script to convert gem5 stats to a Streamline .apc project
ali
September 27th, 2013, 12:23 a.m.
simobject: Fix handling of parents for simobject vectors
ali
October 17th, 2013, 4:58 p.m.
ARM: Decode neon memory instructions.
ali
August 13th, 2010, 9:48 a.m.
Core: Add some documentation about the sim clocks.
ali
April 10th, 2011, 4:49 p.m.
Debug: Add a function to cause the simulator to create a checkpoint from GDB.
ali
May 2nd, 2011, 3:22 p.m.
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
ali
November 3rd, 2011, 1:24 p.m.
prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
ali
January 26th, 2012, 4:25 a.m.
ARM: Don't reset CPUs that are going to be switched in.
ali
March 6th, 2012, 4:17 p.m.
base: split out the VncServer into a VncInput and Server classes
ali
October 24th, 2012, 2:19 p.m.
mem: Remove the IIC replacement policy
ali
November 2nd, 2012, 10:10 a.m.
config: Move CPU handover logic to m5.switchCpus()
ali
January 7th, 2013, 11:24 a.m.
kvm: Basic support for hardware virtualized CPUs
ali
March 8th, 2013, 6:13 a.m.
ARM: Implement CLREX
ali
August 13th, 2010, 9:53 a.m.
ARM: Implement all ARM SIMD instructions.
ali
August 23rd, 2010, 9:29 a.m.
CPU/Cache: Fix some errors exposed by valgrind
ali
September 22nd, 2010, 1:43 a.m.
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
ali
November 8th, 2010, 3:28 p.m.
O3: Support timing translations for O3 CPU fetch.
ali
December 6th, 2010, 3:46 p.m.
ARM: Reset m5 stats when program resets performance counters.
ali
February 11th, 2011, 4:34 p.m.
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