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[Submitted] Core: Add some documentation about the sim clocks.
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ali
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April 10th, 2011, 4:49 p.m.
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[Submitted] ARM: Add vfpv3 support to native trace.
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ali
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May 2nd, 2011, 3:19 p.m.
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[Submitted] CPU: Fix a case where timing simple cpu faults can nest.
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ali
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May 2nd, 2011, 3:20 p.m.
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[Submitted] CPU: Add some useful debug message to the timing simple cpu.
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ali
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May 2nd, 2011, 3:21 p.m.
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[Submitted] Debug: Add a function to cause the simulator to create a checkpoint from GDB.
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ali
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May 2nd, 2011, 3:22 p.m.
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[Submitted] O3: Fix an issue with a load & branch instruction and mem dep squashing
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ali
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May 4th, 2011, 6:37 p.m.
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[Submitted] Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
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ali
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May 4th, 2011, 6:38 p.m.
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[Submitted] ARM: Break up condition codes into normal flags, saturation, and simd.
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ali
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May 4th, 2011, 6:39 p.m.
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[Submitted] ARM: Remove the saturating (Q) condition code from the renamed register.
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ali
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May 4th, 2011, 6:40 p.m.
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[Submitted] ARM: Further break up condition code into NZ, C, V bits.
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ali
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May 4th, 2011, 6:43 p.m.
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[Submitted] ARM: Construct the predicate test register for more instruction programatically.
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ali
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May 4th, 2011, 6:44 p.m.
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[Submitted] ARM: Generate condition code setting code based on which codes are set.
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ali
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May 4th, 2011, 6:45 p.m.
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[Submitted] O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
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ali
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May 16th, 2011, 2:35 p.m.
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[Submitted] O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
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ali
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May 16th, 2011, 2:35 p.m.
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[Submitted] O3: Fix offset calculation into storeQueue buffer for store->load forwarding
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ali
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May 16th, 2011, 2:35 p.m.
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[Submitted] Config: Add support for a Self.all proxy object
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ali
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May 26th, 2011, 7:15 p.m.
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[Submitted] O3: Create a pipeline activity viewer for the O3 CPU model.
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ali
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May 26th, 2011, 7:16 p.m.
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[Submitted] IO: Handle case where ISA Fake device is being used as a fake memory.
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ali
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June 16th, 2011, 1:10 p.m.
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[Submitted] O3: Enable pipelining icache accesses in fetch stage
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ali
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June 16th, 2011, 1:10 p.m.
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[Submitted] Branch predictor: Fixes the tournament branch predictor.
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ali
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June 16th, 2011, 1:10 p.m.
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[Submitted] ARM: Add per-processor interrupt support to GIC.
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ali
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July 13th, 2011, 7:53 a.m.
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[Submitted] Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
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ali
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July 13th, 2011, 7:54 a.m.
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[Submitted] O3: Squash the violator and younger instructions instead not all insts.
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ali
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July 13th, 2011, 8:56 a.m.
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[Submitted] ARM: Implement L2CTLR num cpus register.
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ali
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July 13th, 2011, 8:57 a.m.
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[Submitted] ARM: Add per-cpu local timers for ARM.
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ali
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July 15th, 2011, 9:23 a.m.
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[Submitted] Stats: Add a sparse histogram stat object.
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ali
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July 15th, 2011, 9:34 a.m.
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[Submitted] LSQ: Fix a few issues with the storeset predictor.
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ali
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July 15th, 2011, 9:39 a.m.
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[Submitted] LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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ali
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July 26th, 2011, 8:54 a.m.
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[Submitted] Fix bugs due to interaction between SEV instructions and O3 pipeline
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ali
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July 26th, 2011, 8:57 a.m.
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[Submitted] IDE: Fix issues with new PIIX kernel driver and our model.
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ali
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August 9th, 2011, 12:25 p.m.
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[Submitted] ARM: Add VExpress_E support with PCIe to gem5
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ali
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August 9th, 2011, 12:32 p.m.
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[Submitted] Mem: Put prefetcher notify call before packet is deleted.
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ali
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August 9th, 2011, 12:34 p.m.
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[Submitted] LSQ: Only trigger a memory violation with a load/load if the value changes.
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ali
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August 9th, 2011, 12:35 p.m.
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[Submitted] ARM: Mark some variables uncacheable until boot all CPUs are enabled.
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ali
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August 9th, 2011, 12:36 p.m.
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[Submitted] BP: Fix several Branch Predictor issues.
|
ali
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August 19th, 2011, 3:19 p.m.
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[Submitted] gem5ops: Implement Java JNI for gem5Ops
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ali
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August 19th, 2011, 3:19 p.m.
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Regressions: Start of new regression system
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ali
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August 30th, 2011, 10:38 a.m.
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[Submitted] ARM: update TLB to set request packet ASID field
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ali
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September 9th, 2011, 2:49 p.m.
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[Submitted] Prefetch: Don't prefetch if address is in the write queue.
|
ali
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September 9th, 2011, 2:55 p.m.
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[Submitted] O3: Add stat that counts how many cycles the O3 cpu was quiesced.
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ali
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November 3rd, 2011, 1:23 p.m.
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[Submitted] ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .
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ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] Output: Add hierarchical output support and cleanup existing codebase.
|
ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] VNC: Add support for capturing frame buffer to file each time it is changed.
|
ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] ARM: Add support for having a TLB cache.
|
ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] Device: Make changes necessary to support a coherent page walker cache.
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ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
|
ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] CheckerCPU: Re-factor CheckerCPU to be compatible current state of gem5
|
ali
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November 3rd, 2011, 1:27 p.m.
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[Submitted] SE: Change very noise warn message to warn_once
|
ali
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November 16th, 2011, 9:02 p.m.
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[Submitted] sim_cur_ticks: display curTick in stats
|
ali
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December 1st, 2011, 12:29 a.m.
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[Submitted] Base: Fixed shift amount in genrand() to work with large numbers
|
ali
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December 1st, 2011, 12:29 a.m.
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