|
|
[Submitted] Config: Use the attribute naming and include ports in JSON
|
ahansson
|
May 16th, 2012, 7:41 a.m.
|
|
|
|
[Submitted] DMA: Split the DMA device and IO device into seperate files
|
ahansson
|
May 18th, 2012, 5:08 a.m.
|
|
|
|
[Submitted] MEM: Add a snooping DMA port subclass for table walker
|
ahansson
|
May 17th, 2012, 5:05 a.m.
|
|
|
|
[Submitted] Config: Exit with fatal if a port is already connected
|
ahansson
|
May 18th, 2012, 9:10 a.m.
|
|
|
|
[Discarded] Cache: Remove redundant check for uncacheable snoops
|
ahansson
|
May 18th, 2012, 9:12 a.m.
|
|
|
|
[Submitted] MEM: Add the communication monitor
|
ahansson
|
April 20th, 2012, 11:23 a.m.
|
|
|
|
[Submitted] MEM: Do not forward uncacheable to bus snoopers
|
ahansson
|
May 4th, 2012, 9:47 a.m.
|
|
|
|
[Submitted] Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
|
ahansson
|
May 3rd, 2012, 11:22 a.m.
|
|
|
|
[Submitted] MEM: Separate requests and responses for timing accesses
|
ahansson
|
April 11th, 2012, 8:23 a.m.
|
|
|
|
[Submitted] MEM: Use base class Master/SlavePort pointers in the bus
|
ahansson
|
April 9th, 2012, 9:40 a.m.
|
|
|
|
[Submitted] MEM: Add the PortId type and a corresponding id field to Port
|
ahansson
|
April 7th, 2012, 9:51 a.m.
|
|
|
|
[Submitted] clang/gcc: Use STL hash function for int64_t and uint64_t
|
ahansson
|
April 18th, 2012, 9:52 p.m.
|
|
|
|
[Submitted] Ruby: Use MasterPort base-class pointers where possible
|
ahansson
|
April 4th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] MEM: Remove the Broadcast destination from the packet
|
ahansson
|
April 4th, 2012, 12:52 a.m.
|
|
|
|
[Submitted] MEM: Separate snoops and normal memory requests/responses
|
ahansson
|
April 2nd, 2012, 6:49 a.m.
|
|
|
|
[Submitted] Regression: Add ANSI colours to highlight test status
|
ahansson
|
April 6th, 2012, 9:16 a.m.
|
|
|
|
[Submitted] clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
|
ahansson
|
April 2nd, 2012, 12:41 p.m.
|
|
|
|
[Submitted] Ruby: Ensure order-dependent iteration uses an ordered map
|
ahansson
|
April 10th, 2012, 10:18 a.m.
|
|
|
|
[Submitted] MEM: Enable multiple distributed generalized memories
|
ahansson
|
March 21st, 2012, 4:20 p.m.
|
|
|
|
[Submitted] Python: Make the All proxy traverse SimObject children as well
|
ahansson
|
March 21st, 2012, 10:07 a.m.
|
|
|
|
[Submitted] Ruby: Fix the example configurations option parsing
|
ahansson
|
April 4th, 2012, 3:44 p.m.
|
|
|
|
[Submitted] Atomic: Remove the physmem_port and access memory directly
|
ahansson
|
March 20th, 2012, 10:30 a.m.
|
|
|
|
[Submitted] MEM: Remove legacy DRAM in preparation for memory updates
|
ahansson
|
March 21st, 2012, 10:04 a.m.
|
|
|
|
[Submitted] Ruby: Remove the physMemPort and instead access memory directly
|
ahansson
|
March 20th, 2012, 8:31 a.m.
|
|
|
|
[Submitted] MEM: Introduce the master/slave port sub-classes in C++
|
ahansson
|
March 10th, 2012, 11:54 a.m.
|
|
|
|
[Submitted] CPU: Unify initMemProxies across CPUs and simulation modes
|
ahansson
|
March 27th, 2012, 3:55 a.m.
|
|
|
|
[Submitted] range_map: Enable const find and iteration
|
ahansson
|
March 21st, 2012, 10:06 a.m.
|
|
|
|
[Submitted] Power: Change bitfield name to avoid conflicts with range_map
|
ahansson
|
March 21st, 2012, 10:03 a.m.
|
|
|
|
[Submitted] MEM: Unify bus access methods and prepare for master/slave split
|
ahansson
|
February 29th, 2012, 3:06 a.m.
|
|
|
|
[Submitted] MEM: Split SimpleTimingPort into PacketQueue and ports
|
ahansson
|
February 27th, 2012, 2:29 a.m.
|
|
|
|
[Submitted] Scons: Remove Werror=False in SConscript files
|
ahansson
|
March 6th, 2012, 9:18 a.m.
|
|
|
|
[Submitted] gcc: Clean-up of non-C++0x compliant code, first steps
|
ahansson
|
March 6th, 2012, 9:20 a.m.
|
|
|
|
[Submitted] clang: Fix recently introduced clang compilation errors
|
ahansson
|
March 6th, 2012, 9:19 a.m.
|
|
|
|
[Submitted] CPU: Check that the interrupt controller is created when needed
|
ahansson
|
March 2nd, 2012, 4:45 a.m.
|
|
|
|
[Submitted] Stats: Fix the realview regression stats after nvmem move
|
ahansson
|
March 2nd, 2012, 5:56 a.m.
|
|
|
|
[Submitted] Ruby: Rename RubyPort::sendTiming to avoid overriding base class
|
ahansson
|
March 2nd, 2012, 5:55 a.m.
|
|
|
|
[Discarded] CPU: Fix switching in of x86 CPU with interrupt and TLB ports
|
ahansson
|
February 24th, 2012, 10:32 a.m.
|
|
|
|
[Submitted] MEM: Make all the port proxy members const
|
ahansson
|
February 24th, 2012, 12:55 a.m.
|
|
|
|
[Submitted] SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
|
ahansson
|
February 28th, 2012, 4:53 a.m.
|
|
|
|
[Submitted] MEM: Simplify cache ports preparing for master/slave split
|
ahansson
|
February 21st, 2012, 3:21 a.m.
|
|
|
|
[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
|
|
|
[Submitted] Ruby: Simplify tester ports by not using SimpleTimingPort
|
ahansson
|
February 16th, 2012, 10:45 a.m.
|
|
|
|
[Submitted] MEM: Move all read/write blob functions from Port to PortProxy
|
ahansson
|
February 15th, 2012, 5:58 a.m.
|
|
|
|
[Submitted] MEM: Make port proxies use references rather than pointers
|
ahansson
|
February 15th, 2012, 5:56 a.m.
|
|
|
|
[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
|
|
|
[Submitted] CPU: Round-two unifying instr/data CPU ports across models
|
ahansson
|
February 14th, 2012, 10:34 a.m.
|
|
|
|
[Submitted] MEM: Fatal when no port can be found for an address
|
ahansson
|
February 12th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] Script: Fix the scripts that use the num_cpus cache parameter
|
ahansson
|
February 13th, 2012, 2:38 a.m.
|
|
|
|
[Submitted] MEM: Fix master/slave ports in Ruby and non-regression scripts
|
ahansson
|
February 13th, 2012, 11:05 a.m.
|
|
|
|
[Submitted] MEM: Explicit ports and Python binding on CopyEngine
|
ahansson
|
January 18th, 2012, 2:34 a.m.
|
|
