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stats: rework the output portion of stats so that they use python
|
nate
|
May 11th, 2012, 8:50 a.m.
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stats: no C++ output
|
nate
|
May 11th, 2012, 8:50 a.m.
|
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[Discarded] x86 syscall emulation: Add the TCGETS ioctl to the whitelist of tty ioctls that
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marc.orr
|
May 11th, 2012, 10:30 a.m.
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[Submitted] syscall emulation: Enabled getrlimit and getrusage for x86. Added/moved rlimit
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marc.orr
|
May 11th, 2012, 12:08 p.m.
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[Submitted] x86 ISA: Implement the sse3 haddps instruction.
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marc.orr
|
May 11th, 2012, 5:13 p.m.
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ARM: Enable Ruby functionality with ARM FS
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afc32
|
May 12th, 2012, 4:23 p.m.
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[Submitted] Decode: Make the Decoder class defined per ISA.
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gblack
|
May 15th, 2012, 5:54 a.m.
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[Submitted] CPU: Simplify the implementation of the decode cache.
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gblack
|
May 15th, 2012, 5:54 a.m.
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[Submitted] ISA: Make the decode function part of the ISA's decoder.
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gblack
|
May 15th, 2012, 5:55 a.m.
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[Submitted] CPU: Merge the predecoder and decoder.
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gblack
|
May 15th, 2012, 5:55 a.m.
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[Submitted] Config: Use the attribute naming and include ports in JSON
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ahansson
|
May 16th, 2012, 7:41 a.m.
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[Discarded] Resetting/dumping ruby_stats when gem5 stats is reset/dumped
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khaleghzadeh
|
May 16th, 2012, 11:02 a.m.
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[Submitted] regression tester: Fix some bugs in simple-timing-mp-ruby.py.
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marc.orr
|
May 16th, 2012, 6:09 p.m.
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[Submitted] syscall emulation: Add the futex system call.
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marc.orr
|
May 16th, 2012, 8:33 p.m.
|
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regression tester: add tests to exercise m5threads with the x86 ISA.
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marc.orr
|
May 16th, 2012, 8:34 p.m.
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[Discarded] Resetting/dumping ruby_stats when gem5 stats is reset/dumped
|
khaleghzadeh
|
May 16th, 2012, 10:30 p.m.
|
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[Submitted] MEM: Add a snooping DMA port subclass for table walker
|
ahansson
|
May 17th, 2012, 5:05 a.m.
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[Submitted] DMA: Split the DMA device and IO device into seperate files
|
ahansson
|
May 18th, 2012, 5:08 a.m.
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[Submitted] Reset and dump ruby stats along with gem5 stats
|
khaleghzadeh
|
May 18th, 2012, 6:21 a.m.
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[Submitted] Config: Exit with fatal if a port is already connected
|
ahansson
|
May 18th, 2012, 9:10 a.m.
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[Discarded] Cache: Remove redundant check for uncacheable snoops
|
ahansson
|
May 18th, 2012, 9:12 a.m.
|
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|
Hierarchical Network Topology for Ruby
|
khaleghzadeh
|
May 20th, 2012, 11:05 a.m.
|
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regression tester: add tests to exercise m5threads with the x86 ISA.
|
marc.orr
|
May 20th, 2012, 6:38 p.m.
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mthreads regression: Add some more configurations to be tested with m5threads.
|
marc.orr
|
May 20th, 2012, 6:38 p.m.
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[Submitted] Cache: Remove dangling doWriteback declaration
|
ahansson
|
May 23rd, 2012, 6:30 a.m.
|
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[Submitted] Bridge: Split deferred request, response and sender state
|
ahansson
|
May 23rd, 2012, 6:31 a.m.
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[Submitted] Packet: Updated comments for src and dest fields
|
ahansson
|
May 23rd, 2012, 6:32 a.m.
|
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[Submitted] Packet: Unify the use of PortID in packet and port
|
ahansson
|
May 23rd, 2012, 6:32 a.m.
|
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[Submitted] Bus: Turn the PortId into a transport function parameter
|
ahansson
|
May 23rd, 2012, 6:34 a.m.
|
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[Submitted] Config: A patch from Nilay which fixes running SMT workloads with se.py.
|
gblack
|
May 25th, 2012, 12:51 a.m.
|
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[Submitted] ISA,CPU: Generalize and split out the components of the decode cache.
|
gblack
|
May 25th, 2012, 3:33 a.m.
|
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[Submitted] X86: Move address based decode caching in front of the predecoder.
|
gblack
|
May 25th, 2012, 3:44 a.m.
|
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[Submitted] O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
|
atgutier
|
May 25th, 2012, 9:05 a.m.
|
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[Submitted] Bus: Remove redundant packet parameter from isOccupied
|
ahansson
|
May 25th, 2012, 9:47 a.m.
|
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[Submitted] Bus: Split the bus into a non-coherent and coherent bus
|
ahansson
|
May 25th, 2012, 9:47 a.m.
|
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[Submitted] X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.
|
gblack
|
May 27th, 2012, 2:43 p.m.
|
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[Submitted] X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.
|
gblack
|
May 27th, 2012, 2:43 p.m.
|
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[Submitted] X86: Move the GDT down to where it can be accessed in 32 bit mode.
|
gblack
|
May 27th, 2012, 2:44 p.m.
|
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[Submitted] X86: Add a 32 bit hello world test binary.
|
gblack
|
May 27th, 2012, 2:46 p.m.
|
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ISA: Factor FullSystemInt out of the decoders.
|
gblack
|
May 28th, 2012, 12:49 a.m.
|
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[Submitted] SPARC: Keep a copy of the current ASI in the decoder.
|
gblack
|
May 28th, 2012, 2:54 a.m.
|
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[Submitted] ARM: Keep a copy of the fpscr len and stride fields in the decoder.
|
gblack
|
May 28th, 2012, 2:55 a.m.
|
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[Discarded] Decoder: Remove the thread context getting/setting interface from the decoder.
|
gblack
|
May 28th, 2012, 2:57 a.m.
|
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[Submitted] cpu: prevent switched out CPUs from being initialized in the simple and inorder models.
|
atgutier
|
May 28th, 2012, 10:44 a.m.
|
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[Submitted] ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
|
gblack
|
May 29th, 2012, 2:59 a.m.
|
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[Submitted] gcc: Small fixes to compile with gcc 4.7
|
ahansson
|
May 29th, 2012, 8:54 a.m.
|
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[Submitted] sim: Provide a framework for detecting out of data checkpoints and migrating them.
|
ali
|
May 30th, 2012, 9:34 a.m.
|
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|
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[Submitted] sim: Remove FastAlloc
|
ali
|
May 30th, 2012, 10:30 a.m.
|
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[Submitted] O3: Clean up the O3 structures and try to pack them a bit better.
|
ali
|
May 30th, 2012, 3:10 p.m.
|
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[Submitted] TLB: Fix for gcc 4.4.3
|
jayneel
|
May 30th, 2012, 7:48 p.m.
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